Skip to content
This repository has been archived by the owner on Nov 4, 2024. It is now read-only.

Commit

Permalink
Merge pull request #64 from Abdulwadoodd/zc_dev
Browse files Browse the repository at this point in the history 
Add support for `Zcb` instructions from RISC-V code size reduction extension
  • Loading branch information
@neelgala
neelgala authored Aug 21, 2023
2 parents 5cc22db + fd740a1 commit 7843233
Show file tree
Hide file tree
Showing 5 changed files with 585 additions and 1 deletion.
1 change: 1 addition & 0 deletions CHANGELOG.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ Only when a release to the main branch is done, the contents of the WIP-DEV are
versioned header while the `WIP-DEV` is left empty

## [WIP-DEV]
- Added support of Zcb from Code Size Reduction Extension.
- Added support of Standard Atomic (A) Extension (RV32 and RV64), excluding the LR/SC instruction.
- Updating CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release
cadence.
Expand Down
221 changes: 220 additions & 1 deletion riscv_ctg/data/template.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10317,7 +10317,7 @@ czero.nez:
// $comment
// opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val
TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
amoadd.w:
sig:
Expand Down Expand Up @@ -10678,3 +10678,222 @@ amomaxu.d:
// $comment
// opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val
TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
c.lbu:
sig:
stride: 1
sz: 'XLEN/8'
rs1_op_data: *c_regs
rd_op_data: *c_regs
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb
formattype: 'clformat'
rs1_val_data: '[0]'
imm_val_data: 'gen_usign_dataset(2)'
template: |-
// $comment
// opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
c.lhu:
sig:
stride: 1
sz: 'XLEN/8'
rs1_op_data: *c_regs
rd_op_data: *c_regs
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb
formattype: 'clformat'
rs1_val_data: '[0]'
imm_val_data: 'gen_usign_dataset(2)'
template: |-
// $comment
// opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
c.lh:
sig:
stride: 1
sz: 'XLEN/8'
rs1_op_data: *c_regs
rd_op_data: *c_regs
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb
formattype: 'clformat'
rs1_val_data: '[0]'
imm_val_data: 'gen_usign_dataset(2)'
template: |-
// $comment
// opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
c.sb:
sig:
stride: 1
sz: 'XLEN/8'
rs1_op_data: *c_regs
rs2_op_data: *c_regs
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb
formattype: 'csformat'
rs1_val_data: '[0]'
rs2_val_data: 'gen_sign_dataset(xlen)'
imm_val_data: 'gen_usign_dataset(2)'
template: |-
// $comment
// opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
c.sh:
sig:
stride: 1
sz: 'XLEN/8'
rs1_op_data: *c_regs
rs2_op_data: *c_regs
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb
formattype: 'csformat'
rs1_val_data: '[0]'
rs2_val_data: 'gen_sign_dataset(xlen)'
imm_val_data: 'gen_usign_dataset(2)'
template: |-
// $comment
// opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
c.sext.b:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb_Zbb
formattype: 'ckformat'
rs1_op_data: *c_regs
rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
template: |-
// $comment
// opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.sext.h:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb_Zbb
formattype: 'ckformat'
rs1_op_data: *c_regs
rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]'
template: |-
// $comment
// opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.zext.b:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb
formattype: 'ckformat'
rs1_op_data: *c_regs
rs1_val_data: 'gen_usign_dataset(xlen)+[128]'
template: |-
// $comment
// opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.zext.h:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb_Zbb
formattype: 'ckformat'
rs1_op_data: *c_regs
rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
template: |-
// $comment
// opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.zext.w:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [64]
std_op:
isa:
- I_Zca_Zcb_Zba
formattype: 'ckformat'
rs1_op_data: *c_regs
rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
template: |-
// $comment
// opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.not:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [32,64]
std_op:
isa:
- I_Zca_Zcb
formattype: 'kformat'
rs1_op_data: *c_regs
rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
template: |-
// $comment
// opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.mul:
sig:
stride: 1
sz: 'XLEN/8'
rs1_op_data: *c_regs
rs2_op_data: *c_regs
xlen: [32,64]
std_op:
isa:
- IM_Zca_Zcb
formattype: 'crformat'
operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))'
rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
template: |-
// $comment
// opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
2 changes: 2 additions & 0 deletions riscv_ctg/generator.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@ def get_rm(opcode):
'cbformat': ['rs1'],
'cjformat': [],
'kformat': ['rs1','rd'],
'ckformat': ['rs1'],
# 'frformat': ['rs1', 'rs2', 'rd'],
'fsrformat': ['rs1', 'rd'],
# 'fr4format': ['rs1', 'rs2', 'rs3', 'rd'],
Expand Down Expand Up @@ -103,6 +104,7 @@ def get_rm(opcode):
'cbformat': "['rs1_val', 'imm_val']",
'cjformat': "['imm_val']",
'kformat': "['rs1_val']",
'ckformat': "['rs1_val']",
# 'frformat': "['rs1_val', 'rs2_val', 'rm_val', 'fcsr']",
'fsrformat': "['rs1_val', 'fcsr'] + get_rm(opcode) + \
([] if not is_nan_box else ['rs1_nan_prefix'])",
Expand Down
Loading

0 comments on commit 7843233

Please sign in to comment.