Add support for Zfinx and Zfh extension (#67)

* Updated Zfinx sign extension * Updated Zfinx sign extension code * latest Zfh code * Updated latest code * updated Zfinx code * Introduced half width and half word with respect to Zfh * Added RV64Zfh cgf files * Added RV64Zfinx cgf files * Updated the missing ISA regex expression * updated the yaml * Removed unwanted space --------- Signed-off-by: anuani21 <[email protected]> Signed-off-by: Umer Shahid <[email protected]> Co-authored-by: Umer Shahid <[email protected]>
riscv-software-src · Aug 22, 2024 · 9d5e1e5 · 9d5e1e5
1 parent 15c8ee9
commit 9d5e1e5
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Showing 66 changed files with 7,993 additions and 38 deletions.
diff --git a/riscv_ctg/constants.py b/riscv_ctg/constants.py
@@ -191,7 +191,7 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 # increment each value in dataset, increment each value in dataset, add them to the dataset
     return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0
 
-template_fnames = ["template.yaml","imc.yaml","fd.yaml"]
+template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml"]
 
 template_files = [os.path.join(root,"data/"+f) for f in template_fnames]
 

diff --git a/riscv_ctg/ctg.py b/riscv_ctg/ctg.py
@@ -16,7 +16,7 @@
 from math import *
 from riscv_ctg.__init__ import __version__
 
-def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen, flen):
+def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen, flen, inxFlag):
     iflen = 0
     if 'mnemonics' not in node and 'csr_comb' not in node:
         logger.warning("Neither mnemonics nor csr_comb node not found in covergroup: " + str(label))
@@ -42,7 +42,7 @@ def gen_test(op_node, opcode):
             fprefix = os.path.join(out_dir,str(label))
             logger.info('Generating Test for :' + str(label) +"-" + opcode)
             formattype  = op_node['formattype']
-            gen = Generator(formattype,op_node,opcode,randomize,xlen,flen,iflen,base_isa)
+            gen = Generator(formattype,op_node,opcode,randomize,xlen,flen,iflen,base_isa,inxFlag)
             op_comb = gen.opcomb(node)
             val_comb = gen.valcomb(node)
             instr_dict = gen.correct_val(
@@ -100,7 +100,7 @@ def gen_test(op_node, opcode):
         logger.info('Writing tests for csr_comb')
         csr_comb_gen.write_test(fprefix, node, usage_str, label, csr_comb_instr_dict)
 
-def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst):
+def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst,inxFlag):
     logger.level(verbose)
     logger.info('****** RISC-V Compliance Test Generator {0} *******'.format(__version__ ))
     logger.info('Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.')
@@ -123,9 +123,17 @@ def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, ma
     usage_str = const.usage.safe_substitute(base_isa=base_isa, \
             cgf=cgf_argument, version = __version__, time=mytime, \
             randomize=randomize_argument,xlen=str(xlen_arg))
+    # ---------------------------------
+    # IITM Changes
+    # This <inxFlag> is introduced to handle the template conflict over float instructions
+    # ---------------------------------
+    if inxFlag:
+        const.template_files.remove([fd for fd in const.template_files if "fd.yaml" in fd][0])
+    else:
+        const.template_files.remove([fd for fd in const.template_files if "inx.yaml" in fd][0])
     op_template = utils.load_yamls(const.template_files)
     cgf = expand_cgf(cgf_file,xlen,flen)
     pool = mp.Pool(num_procs)
     results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template,
-        randomize, out_dir, xlen, flen) for label,node in cgf.items()])
+        randomize, out_dir, xlen, flen, inxFlag) for label,node in cgf.items()])
     pool.close()