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Updated the yaml and cover group files to accomdate the compreseed fl…
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…oating point
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@anuani21
anuani21 committed Sep 30, 2024
1 parent 0827734 commit b28007b
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Showing 5 changed files with 117 additions and 99 deletions.
77 changes: 43 additions & 34 deletions riscv_ctg/data/imc.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -1894,38 +1894,40 @@ c.flw:
sig:
stride: 1
sz: 'XLEN/8'
rs1_op_data: *all_regs_mx0
rd_op_data: *all_fregs
rs1_op_data: *c_regs
rd_op_data: *c_fregs
xlen: [32]
std_op:
isa:
- IFC
- IF_Zcf
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
formattype: 'clformat'
ea_align_data: '[0,1,2,3]'
rs1_val_data: '[0]'
imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
template: |-
// $comment
// opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
// opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr
TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
c.flwsp:
sig:
stride: 1
sz: 'XLEN/8'
rd_op_data: *all_fregs
rd_op_data: *c_fregs
xlen: [32]
std_op:
isa:
- IFC
- IF_Zcf
formattype: 'ciformat'
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
ea_align_data: '[0,1,2,3]'
imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
template: |-
// $comment
// opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
// opcode: $inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr
TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
Expand All @@ -1934,42 +1936,46 @@ c.fsw:
stride: 1
sz: 'XLEN/8'
xlen: [32]
rs1_op_data: *all_regs_mx0
rs2_op_data: *all_fregs
rs1_op_data: *c_regs
rs2_op_data: *c_fregs
std_op:
isa:
- IFC
- IF_Zcf
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
std_op:
formattype: 'csformat'
ea_align_data: '[0,1,2,3]'
rs1_val_data: '[0]'
rs2_val_data: 'gen_sign_dataset(xlen)'
imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
template: |-
// $comment
// opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
// valreg: $valaddr_reg; valoffset: $val_offset
/* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
valreg: $valaddr_reg; valoffset: $val_offset
*/
TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
c.fswsp:
sig:
stride: 1
sz: 'XLEN/8'
rs2_op_data: *all_fregs
rs2_op_data: *c_fregs
xlen: [32]
std_op:
isa:
- IFC
- IF_Zcf
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
formattype: 'cssformat'
ea_align_data: '[0,1,2,3]'
rs2_val_data: 'gen_sign_dataset(xlen)'
imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
template: |-
// $comment
// opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
// valreg: $valaddr_reg; valoffset: $val_offset
/* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
valreg: $valaddr_reg; valoffset: $val_offset
*/
TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
c.fld:
Expand All @@ -1986,32 +1992,32 @@ c.fld:
xlen: [32,64]
std_op:
isa:
- IFDC
- IFD_Zcd
formattype: 'clformat'
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
ea_align_data: '[0,1,2,3]'
imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
template: |-
// $comment
// opcode:$inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
// opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
c.fldsp:
sig:
stride: 2
sz: 'SIGALIGN'
rd_op_data: *all_fregs
rd_op_data: *c_fregs
xlen: [32,64]
std_op:
isa:
- IFDC
- IFD_Zcd
formattype: 'ciformat'
imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
template: |-
// $comment
// opcode:$inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4
// opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4
TEST_LOAD_F($swreg,$testreg,$fcsr,x2,$rd,$imm_val,$inst,$ea_align,x4)
c.fsd:
Expand All @@ -2026,20 +2032,21 @@ c.fsd:
rs1_op_data: *c_regs
rs2_op_data: *c_fregs
xlen: [32,64]
std_op:
isa:
- IFDC
- IFD_Zcd
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
std_op:
formattype: 'csformat'
ea_align_data: '[0,1,2,3]'
rs2_val_data: 'gen_sign_dataset(xlen)'
imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
template: |-
// $comment
// opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
// valreg: $valaddr_reg; valoffset: $val_offset;
TEST_STORE_F($swreg,$testreg,0,$rs1,$rs2,$imm_val,$offset,$inst,0,$flagreg,$valaddr_reg, $val_offset)
/* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
valreg: $valaddr_reg; valoffset: $val_offset
*/
TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
c.fsdsp:
sig:
Expand All @@ -2050,19 +2057,21 @@ c.fsdsp:
sz: 'FLEN/8'
val_template: "''"
load_instr: "FLREG"
rs2_op_data: *all_fregs
rs2_op_data: *c_fregs
xlen: [32,64]
std_op:
isa:
- IFDC
- IFD_Zcd
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
formattype: 'cssformat'
ea_align_data: '[0,1,2,3]'
rs2_val_data: 'gen_sign_dataset(xlen)'
imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
template: |-
// $comment
// opcode: $inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
// valreg: $valaddr_reg ; valoffset: $val_offset
TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,0,$flagreg,$valaddr_reg,$val_offset)
/* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
valreg: $valaddr_reg; valoffset: $val_offset
*/
TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
17 changes: 13 additions & 4 deletions riscv_ctg/generator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -132,8 +132,8 @@ def get_rm(opcode):
'jformat': "['imm_val']",
'crformat': "['rs1_val', 'rs2_val']",
'cmvformat': "['rs2_val']",
'ciformat': "['rs1_val', 'imm_val']",
'cssformat': "['rs2_val', 'imm_val']",
'ciformat': "[ 'imm_val','fcsr']",
'cssformat': "['rs2_val', 'imm_val','fcsr']",
'ciwformat': "['imm_val']",
'clformat': "['rs1_val', 'imm_val', 'fcsr']",
'cuformat': "['rs1_val']",
Expand Down Expand Up @@ -281,7 +281,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx
self.inxFlag = inxFlag
self.is_sgn_extd = is_sgn_extd

if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw","c.fld","c.flwsp","c.fswsp","c.fldsp","c.fsdsp"]:
if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.fld","c.flwsp","c.fswsp","c.fldsp","c.fsdsp"]:
self.val_vars = self.val_vars + ['ea_align']
self.template = opnode['template']
self.opnode = opnode
Expand Down Expand Up @@ -812,7 +812,11 @@ def gen_inst(self,op_comb, val_comb, cgf):
for y in op_inds[i:]:
if op[y] == op[x]:
val[ind_dict[y]] = val[ind_dict[x]]
if self.is_fext:
if self.is_fext and self.opcode in ['c.flwsp','c.fswsp','c.fldsp','c.fsdsp']:
if any([x == 'x2' for x in op]):
cont.append(val)
instr_dict.append(self.__cmemsp_instr__(op,val))
elif self.is_fext:
instr_dict.append(self.__fext_instr__(op,val))
elif self.opcode == 'c.lui':
instr_dict.append(self.__clui_instr__(op,val))
Expand Down Expand Up @@ -1078,6 +1082,11 @@ def valreg(self,instr_dict):
if self.is_nan_box:
dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)],
instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen)
elif self.is_fext and self.opcode in ['c.flwsp', 'c.fldsp']:
dval = (instr_dict[i]['rs{0}_val'.format(j)],width)
# instr_dict[i]['flagreg'] = available_reg[1]
elif self.is_fext and self.opcode in ['c.fswsp', 'c.fsdsp']:
dval = (instr_dict[i]['rs2_val'.format(j)],width)
else:
dval = (instr_dict[i]['rs{0}_val'.format(j)],width)
if self.is_fext:
Expand Down
2 changes: 1 addition & 1 deletion sample_cgfs/dataset.cgf
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Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ datasets:
x14: 0
x15: 0

c_fregs: &c_fregs
c_fregs: &c_fregs
f8: 0
f9: 0
f10: 0
Expand Down
56 changes: 28 additions & 28 deletions sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf
View file
Original file line number Diff line number Diff line change
@@ -1,38 +1,38 @@
c.flw:
config:
- check ISA:=regex(.*I.*F.*C.*)
- check ISA:=regex(.*I.*F.*Zcf.*)
opcode:
c.flw: 0
rs1:
<<: *c_regs
rd:
<<: *c_fregs
val_comb:
'imm_val > 0 and fcsr == 0': 0
'imm_val == 0 and fcsr == 0': 0
abstract_comb:
'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0
'imm_val > 0 and fcsr == 0': 0
'imm_val == 0 and fcsr == 0': 0
abstract_comb:
'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0

c.flwsp:
config:
- check ISA:=regex(.*I.*F.*C.*)
- check ISA:=regex(.*I.*F.*Zcf.*)
opcode:
c.flwsp: 0
rd:
<<: *c_fregs
val_comb:
'imm_val > 0 and fcsr == 0': 0
'imm_val == 0 and fcsr == 0': 0
abstract_comb:
'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0
'imm_val > 0 and fcsr == 0': 0
'imm_val == 0 and fcsr == 0': 0
abstract_comb:
'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0

c.fsw:
config:
- check ISA:=regex(.*I.*F.*C.*)
- check ISA:=regex(.*I.*F.*Zcf.*)
opcode:
c.fsw: 0
rs1:
Expand All @@ -42,24 +42,24 @@ c.fsw:
op_comb:
'rs1 != rs2': 0
val_comb:
'imm_val > 0': 0
'imm_val == 0': 0
abstract_comb:
'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0
'imm_val > 0': 0
'imm_val == 0': 0
abstract_comb:
'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0

c.fswsp:
config:
- check ISA:=regex(.*I.*F.*C.*)
- check ISA:=regex(.*I.*F.*Zcf.*)
opcode:
c.fswsp: 0
rs2:
<<: *c_fregs
val_comb:
'imm_val > 0': 0
'imm_val == 0': 0
abstract_comb:
'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0
'imm_val > 0': 0
'imm_val == 0': 0
abstract_comb:
'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0
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