Merge pull request #44 from edwin7026/master

Support for cross combination coverpoint test generation

CHANGELOG.md

@@ -2,6 +2,9 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.9.0] - 2022-08-25
+- Added support for cross_comb coverpoint test generation
+
 ## [0.8.0] - 2022-08-08
 - Added support for a distributed template database.
 - Added generic mechanisms to generate data sections based on test instances.

docs/source/cross_comb.rst

@@ -0,0 +1,35 @@
+************************************************
+Test Generation using Cross Coverage Coverpoints
+************************************************
+
+Coverpoints constituting multiple instructions can help identify interesting instruction
+sequences which have architectural significance such as structural hazards and data hazards.
+The coverpoint node associated with the test generation is ``cross_comb`` defined `here <https://riscv-isac.readthedocs.io/en/stable/cgf.html>`_.
+
+The test generator employs a constraint solver to generate relevant instruction sequence for a
+``cross_comb`` coverpoint.
+
+Example
+-------
+
+    **Coverpoint Definition**
+
+    An example cross combination coverpoint is given below: ::
+
+        add:
+            cross_comb:
+                "[add : ? : rv32i_arith : ? : sub] :: [a=rd : ? : ? : ? : ?] :: [? : rs1==a or rs2==a : rs1==a or rs2==a : rs1==a or rs2==a : rd==a]"
+
+    **Possible assembly sequence**
+
+    A possible sequence of instructions CTG would generate is: ::
+    
+        add x3, x3, x4
+        addi x5, x3, 1
+        sub x6, x4, x3
+        addi x4, x3, -3
+        sub x3, x5, x6
+
+The test generator also embeds appropriate macros for initialization of registers and signature region pointing registers.
+
+Note: The cross-combination test generator as of now, does not support load, store and branch instructions

riscv_ctg/__init__.py

@@ -4,5 +4,5 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = '[email protected]'
-__version__ = '0.8.0'
+__version__ = '0.9.0'
 

riscv_ctg/constants.py

@@ -217,6 +217,10 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 // This assembly file tests the $opcode instruction of the RISC-V $extension extension for the $label covergroup.
 // '''
 
+cross_comment_template = '''
+// This assembly file is used for the test of cross-combination coverpoint described in $label covergroup.
+'''
+
 test_template = Template(copyright_string + comment_template+'''
 #include "model_test.h"
 #include "arch_test.h"
@@ -240,6 +244,31 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 $sig
 RVMODEL_DATA_END
 ''')
+
+cross_test_template = Template(copyright_string + cross_comment_template+'''
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("$isa")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+$test
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+$data
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+$sig
+RVMODEL_DATA_END
+''')
+
 case_template = Template('''
 RVTEST_CASE($num,"//$cond;def TEST_CASE_1=True;",$cov_label)
 ''')