Fixed rs2 register for fs* instructions.

riscv-software-src · Aug 8, 2022 · 05b9128 · 05b9128
1 parent c821409
commit 05b9128
Showing 1 changed file with 12 additions and 12 deletions.
diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py
@@ -780,7 +780,7 @@ def arithi_ops(self, instrObj):
 
         return instrObj
 
-    # Put the following function in internaldecoder.py 
+    # Put the following function in internaldecoder.py
     def rvp_ops(self, instrObj):
 
         instr = instrObj.instr
@@ -1223,7 +1223,7 @@ def arith_ops(self, instrObj):
                 instrObj.instr_name = 'min'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
-                instrObj.rd = rd  
+                instrObj.rd = rd
             elif funct7 == 0b0010000:
                 instrObj.instr_name = 'sh2add'
                 instrObj.rs1 = rs1
@@ -1234,7 +1234,7 @@ def arith_ops(self, instrObj):
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
                 instrObj.rd = rd
-                
+
             # elif funct7 == 0b0100100:
             #     instrObj.instr_name = 'packu'
             #     instrObj.rs1 = rs1
@@ -1262,7 +1262,7 @@ def arith_ops(self, instrObj):
                 instrObj.instr_name = 'minu'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
-                instrObj.rd = rd  
+                instrObj.rd = rd
             elif funct7 == 0b0100100:
                 instrObj.instr_name = 'bext'
                 instrObj.rs1 = rs1
@@ -1280,12 +1280,12 @@ def arith_ops(self, instrObj):
                 instrObj.instr_name = 'sh3add'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
-                instrObj.rd = rd  
+                instrObj.rd = rd
             elif funct7 == 0b0000101:
                 instrObj.instr_name = 'max'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
-                instrObj.rd = rd  
+                instrObj.rd = rd
             else:
                 instrObj.instr_name = 'or'
 
@@ -1429,7 +1429,7 @@ def rv64i_arithi_ops(self, instrObj):
                     instrObj.instr_name = 'sraiw'
 
         return instrObj
-        
+
     def rv64m_arithm_ops(self, instrObj):
         instr = instrObj.instr
         funct3 = (instr & self.FUNCT3_MASK) >> 12
@@ -1535,8 +1535,8 @@ def rv64i_arith_ops(self, instrObj):
                 instrObj.instr_name = 'sh3add.uw'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
-                instrObj.rd = rd 
-        
+                instrObj.rd = rd
+
 
         return instrObj
 
@@ -1629,7 +1629,7 @@ def fsw_fsd(self, instrObj):
         imm_4_0 = (instr & self.RD_MASK) >> 7
         imm_11_5 = (instr >> 25) << 5
         imm = self.twos_comp(imm_4_0 + imm_11_5, 12)
-        rs1 = ((instr & self.RS1_MASK) >> 15, 'd')
+        rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
         rs2 = ((instr & self.RS2_MASK) >> 20, 'f')
 
         funct3 = (instr & self.FUNCT3_MASK) >> 12
@@ -1972,7 +1972,7 @@ def rv32_rv64_float_ops(self, instrObj):
             instrObj.rs1 = (rs1[0], 'x')
             instrObj.rs2 = None
             return instrObj
-        
+
         if instrObj.instr_name != 'None':
             return instrObj
 
@@ -2329,7 +2329,7 @@ def quad2(self, instrObj):
             instrObj.rs1 = (2 , 'x')
         return instrObj
 
-    
+
 
     def parseCompressedInstruction(self, instrObj_temp):
         ''' Parse a compressed instruction