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Minor bug fix in compressed immediate decoding #74

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Minor bug fix in compressed immediate decoding #74

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dd56d0a
Update rvopcodesdecoder.py
mahendraVamshi Jul 28, 2023
91d0c0b
Bump version: 0.18.0 → 0.18.1
mahendraVamshi Jul 31, 2023
6a9dea0
minor changes
mahendraVamshi Jul 31, 2023
29599e2
Update rvopcodesdecoder.py
mahendraVamshi Aug 10, 2023
a91da56
Revert "Update rvopcodesdecoder.py"
mahendraVamshi Sep 21, 2023
73acdc1
Update spike.py
mahendraVamshi Sep 29, 2023
eaa6404
Update rvopcodesdecoder.py
mahendraVamshi Oct 13, 2023
3e17fc6
Update rvopcodesdecoder.py
mahendraVamshi Oct 13, 2023
b43aacd
experiment
mahendraVamshi Oct 17, 2023
abbe92e
exp
mahendraVamshi Oct 17, 2023
93a5b4a
exp
mahendraVamshi Oct 17, 2023
5deaf26
exp
mahendraVamshi Oct 17, 2023
e2f8e62
revert back
mahendraVamshi Oct 17, 2023
2b5343e
Update rvopcodesdecoder.py
mahendraVamshi Oct 17, 2023
d592747
Update rvopcodesdecoder.py
mahendraVamshi Oct 18, 2023
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3 changes: 3 additions & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,9 @@

This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## [0.18.1] - 2023-07-31
- Minor fix to compressed immediate decoding

## [0.18.0] - 2023-07-26
- Add support to decode compressed instructions

Expand Down
2 changes: 1 addition & 1 deletion riscv_isac/__init__.py
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Expand Up @@ -4,5 +4,5 @@

__author__ = """InCore Semiconductors Pvt Ltd"""
__email__ = '[email protected]'
__version__ = '0.18.0'
__version__ = '0.18.1'

183 changes: 103 additions & 80 deletions riscv_isac/data/rvopcodesdecoder.py
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Expand Up @@ -355,22 +355,34 @@ def decode(self, instrObj_temp):
for arg in args[:-1]:
if 'rd' in arg:
treg = reg_type
if any([instr_name.startswith(x) for x in [
'fcvt.w','fcvt.l','fmv.s','fmv.d','flt','feq','fle','fclass']]):
treg = 'x'
temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), treg)
if 'p' in arg:
temp_instrobj.rd = (8+int(get_arg_val(arg)(mcode), 2), treg)
else:
if any([instr_name.startswith(x) for x in [
'fcvt.w','fcvt.l','fmv.s','fmv.d','flt','feq','fle','fclass']]):
treg = 'x'
temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), treg)
if 'rs1' in arg:
treg = reg_type
if any([instr_name.startswith(x) for x in [
'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
treg = 'x'
temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'p' in arg:
temp_instrobj.rs1 = (8+int(get_arg_val(arg)(mcode), 2), treg)
else:
if any([instr_name.startswith(x) for x in [
'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
treg = 'x'
temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'rs2' in arg:
treg = reg_type
temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'p' in arg:
temp_instrobj.rs2 = (8+int(get_arg_val(arg)(mcode), 2), treg)
else:
temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'rs3' in arg:
treg = reg_type
temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'p' in arg:
temp_instrobj.rs3 = (8+int(get_arg_val(arg)(mcode), 2), treg)
else:
temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'csr' in arg:
temp_instrobj.csr = int(get_arg_val(arg)(mcode), 2)
if arg == 'shamt':
Expand Down Expand Up @@ -418,114 +430,122 @@ def decode(self, instrObj_temp):
imm = imm[0] + imm_temp[-1] + imm[1:] + imm_temp[0:4] + '0'
else:
imm = imm + imm_temp
if arg == 'c_uimm7hi':

if arg == 'c_uimm7hi': # zero extended
# offset[5:3]
imm_temp = get_arg_val(arg)(mcode)
if imm:
# scalling by factor 4 ('00') if lower 2 bits are got already
imm = imm[-1] + imm_temp + imm[0] + '00'
else:
imm = imm_temp + imm
if arg == 'c_uimm7lo':
if arg == 'c_uimm7lo':
# offest[2|6]
imm_temp = get_arg_val(arg)(mcode)
if imm:
# scalling by factor 4 ('00') if higher 3 bits are got already
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
else:
imm = imm + imm_temp

if arg == 'c_uimm8lo':
if arg == 'c_uimm8lo':
# offest[7:6]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
# scalling by factor 8 ('000') if higher 3 bits are got already
imm = imm_temp + imm + '000'
else:
imm = imm + imm_temp
if arg == 'c_uimm8hi':
if arg == 'c_uimm8hi': # zero extended
imm_temp = get_arg_val(arg)(mcode)
# offest[5:3]
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
# scalling by factor 8 ('000') if lower 2 bits are got already
imm = imm + imm_temp + '000'
else:
imm = imm_temp + imm

if arg == 'c_uimm9lo':
# offest[7:6]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
# scalling by factor 16 ('0000') if higher 3 bits are got already
imm = imm[-1] + imm_temp + imm[0:2] +'0000'
else:
imm = imm + imm_temp
elif arg == 'c_uimm9hi':
elif arg == 'c_uimm9hi': # zero extended
# offest[5:4|8]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
# scalling by factor 16 ('0000') if lower 2 bits are got already
imm = imm_temp[-1] + imm + imm_temp[0:2] +'0000'
else:
imm = imm_temp + imm

elif arg == 'c_nzimm6lo':
# offest[4:0]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
else:
imm = imm + imm_temp
# concatenate offset[5] to offset[4:0]
imm = imm + imm_temp
elif arg == 'c_nzimm6hi':
# offest[5]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
else:
imm = imm_temp + imm
# concatenate offset[4:0] to offset[5]
imm = imm_temp + imm

elif arg == 'c_imm6lo':
# offest[4:0]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
else:
imm = imm + imm_temp
# concatenate offset[5] to offset[4:0]
imm = imm + imm_temp
elif arg == 'c_imm6hi':
# offest[5]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
else:
imm = imm_temp + imm
# concatenate offset[4:0] to offset[5]
imm = imm_temp + imm

elif arg == 'c_nzimm10hi':
# offset[9]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
imm = imm_temp + imm[2:4] + imm[1] + imm[4] + imm[0]
else:
imm = imm_temp + imm
elif arg == 'c_nzimm10lo':
# offset[4|6|8:7|5]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
imm = imm + imm_temp[2:4] + imm_temp[1] + imm_temp[4] + imm_temp[0]
else:
imm = imm + imm_temp

elif arg == 'c_nzimm18hi':
# offest[17]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
else:
imm = imm_temp + imm
# concatenate offset[16:12] to offset[17]
imm = imm_temp + imm
elif arg == 'c_nzimm18lo':
# offest[16:12]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
else:
imm = imm + imm_temp
# concatenate offset[17] to offset[16:12]
imm = imm + imm_temp

elif arg == 'c_imm12':
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
else:
imm = imm_temp + imm

# offset[11|4|9:8|10|6|7|3:1|5] + '0' (jump)
imm = imm_temp[0] + imm_temp[4] + imm_temp[2:4] + imm_temp[6] + imm_temp[5] + imm_temp[10] + imm_temp[1] +imm_temp[7:11] + '0'
elif arg == 'c_bimm9lo':
imm_temp = get_arg_val(arg)(mcode)
# offset[7:6|2:1|5] + '0' (branch)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
imm = imm[0] + imm_temp[0:2] + imm_temp[4] + imm[1:3] + imm_temp[2:4] + '0'
else:
imm = imm + imm_temp
elif arg == 'c_bimm9hi':
# offset[8|4:3]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
imm = imm_temp[0] + imm[0:2] + imm[4] + imm_temp[1:3] + imm[2:4] + '0'
else:
imm = imm_temp + imm

Expand All @@ -534,77 +554,80 @@ def decode(self, instrObj_temp):
imm = imm_temp + imm

elif arg == 'c_nzuimm6lo':
# offest[4:0]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
else:
imm = imm + imm_temp
imm = imm + imm_temp


elif arg == 'c_nzuimm6hi':
# offest[5]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
else:
imm = imm_temp + imm
imm = imm_temp + imm

elif arg == 'c_uimm8splo':
# offset[4:2|7:6] and scalling by 4 ('00')
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
imm = imm_temp[3:5] + imm + imm_temp[0:3] + '00'
else:
imm = imm + imm_temp

elif arg == 'c_uimm8sphi':
elif arg == 'c_uimm8sphi': # zero extended
# offset[5] and scalling by 4 ('00')
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
imm = imm[3:5] + imm_temp + imm[0:3] + '00'
else:
imm = imm_temp + imm

elif arg == 'c_uimm8sp_s':
elif arg == 'c_uimm8sp_s': # zero extended
# offset[5:2|7:6] and scalling by 4 ('00')
imm_temp = get_arg_val(arg)(mcode)
imm = imm[-1] + imm_temp + imm[0] + '00'
imm = imm_temp[4:] + imm_temp[0:4] + '00'

elif arg == 'c_uimm10splo':
elif arg == 'c_uimm10splo':
# offset[4|9:6]
imm_temp = get_arg_val(arg)(mcode)
# scalling by 16 ('0000')
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
imm = imm_temp[1:] + imm + imm_temp[0] + '0000'
else:
imm = imm + imm_temp

elif arg == 'c_uimm10sphi':
elif arg == 'c_uimm10sphi': # zero extended
# offset[5]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
imm = imm[1:] + imm_temp + imm[0] + '0000'
else:
imm = imm_temp + imm

elif arg == 'c_uimm9splo':
# offset[4:3|8:6]
imm_temp = get_arg_val(arg)(mcode)
# scalling by 8 ('000')
if imm:
imm = imm_temp[-1] + imm + imm_temp[0] + '00'
imm = imm_temp[2:] + imm + imm_temp[0:2] + '000'
else:
imm = imm + imm_temp

elif arg == 'c_uimm9sphi':
elif arg == 'c_uimm9sphi': # zero extended
# offset[5]
imm_temp = get_arg_val(arg)(mcode)
if imm:
imm = imm[-1] + imm_temp + imm[0] + '00'
imm = imm[2:] + imm_temp + imm[0:2] + '000'
else:
imm = imm_temp + imm

elif arg == 'c_uimm10sp_s':
imm_temp = get_arg_val(arg)(mcode)
imm = imm_temp + imm

elif arg == 'c_uimm9sp_s':
elif arg == 'c_uimm10sp_s': # zero extended
# offset[5:4|9:6] and scalling by 16 ('0000')
imm_temp = get_arg_val(arg)(mcode)
imm = imm_temp + imm
imm = imm_temp[2:] + imm_temp[0:2] + '0000'

elif arg == 'c_nzuimm10':
elif arg == 'c_uimm9sp_s': # zero extended
# offset[5:3|8:6] and scalling by 8 ('000')
imm_temp = get_arg_val(arg)(mcode)
imm = imm_temp + imm
imm = imm_temp[3:] + imm_temp[0:3] + '000'

if imm:
numbits = len(imm)
Expand Down
2 changes: 1 addition & 1 deletion riscv_isac/plugins/spike.py
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Expand Up @@ -15,7 +15,7 @@ def setup(self, trace, arch):
'[0-9]\s(?P<addr>[0-9abcdefx]+)\s\((?P<instr>[0-9abcdefx]+)\)')
instr_pattern_spike_xd = re.compile(
'[0-9]\s(?P<addr>[0-9abcdefx]+)\s\((?P<instr>[0-9abcdefx]+)\)' +
'\s(?P<regt>[xf])(?P<reg>[\s|\d]\d)\s(?P<val>[0-9abcdefx]+)'
'\s(?P<regt>[xf])(?P<reg>[\s|\d]+)\s(?P<val>[0-9abcdefx]+)'
)

def extractInstruction(self, line):
Expand Down
2 changes: 1 addition & 1 deletion setup.cfg
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@@ -1,5 +1,5 @@
[bumpversion]
current_version = 0.18.0
current_version = 0.18.1
commit = True
tag = True

Expand Down
2 changes: 1 addition & 1 deletion setup.py
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Expand Up @@ -26,7 +26,7 @@ def read_requires():

setup(
name='riscv_isac',
version='0.18.0',
version='0.18.1',
description="RISC-V ISAC",
long_description=readme + '\n\n',
classifiers=[
Expand Down
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