Merged in Dave's RVA23/RVB23. Adding lots of extensions. Still in pro…

…gress.

Rakefile

@@ -359,6 +359,10 @@ task :portfolios do
   Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke
   portfolio_start_msg("RVA22")
   Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke
+  portfolio_start_msg("RVA23")
+  Rake::Task["#{$root}/gen/profile_doc/pdf/RVA23.pdf"].invoke
+  portfolio_start_msg("RVB23")
+  Rake::Task["#{$root}/gen/profile_doc/pdf/RVB23.pdf"].invoke
 end
 
 def portfolio_start_msg(name)
@@ -381,3 +385,5 @@ task "MockProfileRelease": "#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"
 task "RVI20": "#{$root}/gen/profile_doc/pdf/RVI20.pdf"
 task "RVA20": "#{$root}/gen/profile_doc/pdf/RVA20.pdf"
 task "RVA22": "#{$root}/gen/profile_doc/pdf/RVA22.pdf"
+task "RVA23": "#{$root}/gen/profile_doc/pdf/RVA23.pdf"
+task "RVB23": "#{$root}/gen/profile_doc/pdf/RVB23.pdf"

arch/ext/S.yaml

@@ -18,6 +18,12 @@ versions:
   requires:
     name: U
     version: "= 1.0.0"
+- version: "1.13.0"
+  state: ratified
+  ratification_date: null
+  requires:
+    name: U
+    version: "= 1.0.0"
 description: |
   This chapter describes the RISC-V supervisor-level architecture, which
   contains a common core that is used with various supervisor-level

arch/ext/Smmpm.yaml

@@ -0,0 +1,21 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Smmpm
+long_name: Pointer masking for M-mode
+description: |
+  A machine-level extension that provides pointer masking for M-mode.
+type: privileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null
+params:
+  PMLEN:
+    description: |
+      The number of high-order bits of an address that are masked by the
+      pointer masking facility.
+    schema:
+      type: integer
+    also_defined_in: [Ssnpm, Smmpm]

arch/ext/Smnpm.yaml

@@ -0,0 +1,22 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Smnpm
+long_name: Pointer masking for next privilege level less than M-mode
+description: |
+  A machine-level extension that provides pointer masking for the next lower privilege mode
+  (S/HS if S-mode is implemented, or U-mode otherwise).
+type: privileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null
+params:
+  PMLEN:
+    description: |
+      The number of high-order bits of an address that are masked by the
+      pointer masking facility.
+    schema:
+      type: integer
+    also_defined_in: [Ssnpm, Smmpm]

arch/ext/Ssnpm.yaml

@@ -0,0 +1,22 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Ssnpm
+long_name: Pointer masking for next privilege level less than S-mode
+description: |
+  A supervisor-level extension that provides pointer masking for the next lower privilege mode (U-mode),
+  and for VS-modes and VU-modes if the H extension is present.
+type: privileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null
+params:
+  PMLEN:
+    description: |
+      The number of high-order bits of an address that are masked by the
+      pointer masking facility.
+    schema:
+      type: integer
+    also_defined_in: [Smnpm, Smmpm]

arch/ext/Sspm.yaml

@@ -0,0 +1,20 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Sspm
+long_name: Pointer masking available in supervisor mode
+description: |
+  Indicates that there is pointer-masking support available in supervisor mode,
+  with some facility provided in the application execution environment to control pointer masking.
+
+  This extension describes an execution environment but has no bearing on hardware implementations.
+  It is intended to be used in profile specifications where a Supervisor profile
+  can only reference Supervisor level pointer masking functionality,
+  and not the associated CSR controls that exist at a higher privilege level (i.e., in the execution environment).
+
+type: privileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null

arch/ext/Ssstrict.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Ssstrict
+long_name: Unimplemented reserved encodings trap and no no-conforming extensions
+description: |
+  No non-conforming extensions are present.  Attempts to
+  execute unimplemented opcodes or access unimplemented CSRs in the
+  standard or reserved encoding spaces raises an illegal instruction
+  exception that results in a contained trap to the supervisor-mode
+  trap handler.
+
+  [NOTE] Ssstrict does not prescribe behavior for the custom encoding
+  spaces or CSRs.
+
+  [NOTE] Ssstrict definition applies to the execution environment
+  claiming to be RVA23/RVB23-compatible.
+  If the hypervisor extension is present, that execution environment will take a contained trap to
+  supervisor-mode (however that trap is implemented, including, but not
+  limited to, emulation/delegation in the outer execution
+  environment). Ssstrict (and all the other RVA23/RVB23 mandates and options)
+  do not apply to any guest VMs run by a hypervisor. An RVA23/RVB23 hypervisor
+  can provide guest VMs that are also RVA23/RVB23-compatible but with an
+  expanded set of emulated standard instructions. An RVA23/RVB23 hypervisor
+  can also choose to implement guest VMs that are not RVA23/RVB23 compatible
+  (e.g., lacking H, or only RVA20).
+
+  [NOTE] Ssstrict is a new RVA23/RVB23 profile-defined extension that restricts the
+  behavior of reserved encoding spaces.  The extension will be added to
+  the supervisor chapter of the privileged architecture.
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null

arch/ext/Supm.yaml

@@ -0,0 +1,20 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Supm
+long_name: Pointer masking available in user mode
+description: |
+  Indicates that there is pointer-masking support available in user mode,
+  with some facility provided in the application execution environment to control pointer masking.
+
+  This extension describes an execution environment but has no bearing on hardware implementations.
+  It is intended to be used in profile specifications where a User profile
+  can only reference User level pointer masking functionality,
+  and not the associated CSR controls that exist at a higher privilege level (i.e., in the execution environment).
+
+type: privileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null

arch/ext/Za64rs.yaml

@@ -0,0 +1,25 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Za64rs
+long_name: Reservation set requirement for RVA profiles
+description: |
+  Reservation sets must be contiguous, naturally aligned, and at most 64 bytes in size.
+
+  [NOTE]
+  This extension was ratified as part of the RVA22 profile.
+
+  [NOTE]
+  The minimum reservation set size is effectively determined by the size of atomic accesses in
+  the A extension.
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null
+    param_constraints:
+      LRSC_RESERVATION_STRATEGY:
+        schema:
+          oneOf:
+            - const: reserve exactly enough to cover the access
+            - const: reserve naturally-aligned 64-byte region

arch/ext/Zama16b.yaml

@@ -0,0 +1,19 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zama16b
+long_name: Misaligned load/store/AMO within aligned 16-byte address are atomic
+description: |
+  Misaligned loads, stores, and AMOs to main memory regions that do not cross a
+  naturally-aligned 16-byte boundary are atomic.
+
+  [NOTE] Zama16b is a new RVA23 profile-defined extension that represents
+  the presence of the new Misaligned Atomicity Granule feature added in
+  Sm1p13.  The extension will be added to the PMA section of the
+  privileged architecture manual.
+
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null

arch/ext/Zcmop.yaml

@@ -0,0 +1,53 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zcmop
+long_name: 16-bit May-be Operations
+description: |
+  The "Zcmop" extension, which defines eight 16-bit MOP
+  instructions named C.MOP.__n__, where __n__ is an odd integer between 1 and
+  15, inclusive.  C.MOP.__n__ is encoded in the reserved encoding space
+  corresponding to C.LUI x__n__, 0, as shown in <<tab:c-mop>>.
+  Unlike the MOPs defined in the Zimop extension, the C.MOP.__n__ instructions
+  are defined to _not_ write any register.
+  Their encoding allows future extensions to define them to read register
+  `x[__n__]`.
+
+  The Zcmop extension depends upon the Zca extension.
+
+  NOTE: Very few suitable 16-bit encoding spaces exist.  This space was chosen
+  because it already has unusual behavior with respect to the `rd`/`rs1`
+  field--it encodes `c.addi16sp` when the field contains `x2`--and is
+  therefore of lower value for most purposes.
+
+  [[tab:c-mop]]
+  .C.MOP.__n__ instruction encoding.
+
+  |===
+  |Mnemonic | Encoding           | Redefinable to read register
+
+  |C.MOP.1  | `0110000010000001` | `x1`
+  |C.MOP.3  | `0110000110000001` | `x3`
+  |C.MOP.5  | `0110001010000001` | `x5`
+  |C.MOP.7  | `0110001110000001` | `x7`
+  |C.MOP.9  | `0110010010000001` | `x9`
+  |C.MOP.11 | `0110010110000001` | `x11`
+  |C.MOP.13 | `0110011010000001` | `x13`
+  |C.MOP.15 | `0110011110000001` | `x15`
+  |===
+
+  NOTE: The recommended assembly syntax for C.MOP.__n__ is simply the nullary
+  C.MOP.__n__.  The possibly accessed register is implicitly `x__n__`.
+
+  NOTE: The expectation is that each Zcmop instruction is equivalent to some
+  Zimop instruction, but the choice of expansion (if any) is left to the
+  extension that redefines the MOP.
+  Note, a Zcmop instruction that does not write a value can expand into a write
+  to `x0`.
+type: unprivileged
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null
+    requires: C

arch/ext/Ziccamoc.yaml

@@ -0,0 +1,18 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Ziccamoc
+long_name: Cacheable and coherent PMAs provide `AMOCASQ` level PMA support
+description: |
+  Main memory regions with both the cacheability and coherence PMAs
+  must provide `AMOCASQ` level PMA support.
+
+  [NOTE] Ziccamoc is a new RVA23 profile-defined extension that ensures
+  Compare and Swap instructions are properly supported in main memory
+  regions.  The extension will be added to the PMA section of the
+  privileged architecture manual.
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: null