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Signed-off-by: james-ball-qualcomm <[email protected]>
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james-ball-qualcomm authored Nov 17, 2024
2 parents cec5c43 + c550227 commit 2cb42b3
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61 changes: 32 additions & 29 deletions arch/certificate_class/MC.yaml
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MC:
name: MC
long_name: Microcontroller Certificate Class
# yaml-language-server: $schema=../../schemas/cert_class_schema.json

introduction: |
This certification class specifies requirements for microcontrollers.
It targets microcontrollers running low-level software on an RTOS or bare-metal.
This CRD is not intended for the smallest possible microcontrollers but rather for applications
benefiting from a standardized microcontroller.
See the https://docs.google.com/document/d/133SZKc18tLsQcT1o6gEmBUkjwrtg2ow63me54RQ1jiY[RISC-V CRDs]
document for information relevant to all RISC-V CRDs.
$schema: cert_class_schema.json#
kind: certificate class
name: MC
long_name: Microcontroller Certificate Class

naming_scheme: |
The MC (M = Microcontroller, C = Certificate) has the following naming scheme (suffixes after MC
are optional but in the below order):
introduction: |
This certification class specifies requirements for microcontrollers.
It targets microcontrollers running low-level software on an RTOS or bare-metal.
This CRD is not intended for the smallest possible microcontrollers but rather for applications
benefiting from a standardized microcontroller.
See the https://docs.google.com/document/d/133SZKc18tLsQcT1o6gEmBUkjwrtg2ow63me54RQ1jiY[RISC-V CRDs]
document for information relevant to all RISC-V CRDs.
MC<model>[v<version>]
naming_scheme: |
The MC (M = Microcontroller, C = Certificate) has the following naming scheme (suffixes after MC
are optional but in the below order):
Where:
MC<model>[v<version>]
* Left & right square braces denote optional.
* \<model> is a 3 digit integer. It is changed only when mandatory extensions are added to a CRD.
** The one's digit is incremented when a small mandatory extension is added (e.g., Zicond)
** The ten's digit is incremented when a medium mandatory extension is addded (e.g., PMP)
** The hundreds's digit is incremented when a large mandatory extension is addded (e.g., V or H)
* \<version> is a semantic version (see semver.org) formatted as <major>[.<minor>.[patch]]. If \<version> is omitted, the reference applies equally to all versions.
** A <major> release indicates support for a new optional extension.
** A <minor> release indicates one or more of the following changes to the certification tests associated with the CRD.
*** Fix test bug or increase test coverage
*** Add more allowed parameter values
*** Support new extension version
** A <patch> release indicates just CRD specification changes without any difference in functional behavior
Where:
mandatory_priv_modes:
- M
* Left & right square braces denote optional.
* \<model> is a 3 digit integer. It is changed only when mandatory extensions are added to a CRD.
** The one's digit is incremented when a small mandatory extension is added (e.g., Zicond)
** The ten's digit is incremented when a medium mandatory extension is addded (e.g., PMP)
** The hundreds's digit is incremented when a large mandatory extension is addded (e.g., V or H)
* \<version> is a semantic version (see semver.org) formatted as <major>[.<minor>.[patch]]. If \<version> is omitted, the reference applies equally to all versions.
** A <major> release indicates support for a new optional extension.
** A <minor> release indicates one or more of the following changes to the certification tests associated with the CRD.
*** Fix test bug or increase test coverage
*** Add more allowed parameter values
*** Support new extension version
** A <patch> release indicates just CRD specification changes without any difference in functional behavior
mandatory_priv_modes:
- M
22 changes: 12 additions & 10 deletions arch/certificate_class/MockCertificateClass.yaml
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MockCertificateClass:
name: MockCertificateClass
long_name: Mock Certificate Class Long Name
# yaml-language-server: $schema=../../schemas/cert_class_schema.json

introduction: |
Here's the Mock Certificate Class introduction.
$schema: cert_class_schema.json#
kind: certificate class
name: MockCertificateClass
long_name: Mock Certificate Class Long Name

naming_scheme: |
Here's the Mock Certificate Class naming scheme.
introduction: |
Here's the Mock Certificate Class introduction.
mandatory_priv_modes:
- M
naming_scheme: |
Here's the Mock Certificate Class naming scheme.
A Mock certificate class or model can have any name as long as it can be a hash key.
description: Here's the Mock Certificate Class description.
mandatory_priv_modes:
- M
261 changes: 131 additions & 130 deletions arch/certificate_model/MC100.yaml
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# yaml-language-server: $schema=../../schemas/testplan_schema.json
# yaml-language-server: $schema=../../schemas/cert_model_schema.json

MC100:
name: MC100
long_name: Basic Microcontroller Certificate
class: MC
model: 100
$schema: cert_model_schema.json#
kind: certificate model
name: MC100
long_name: Basic Microcontroller Certificate
class:
$ref: certificate_class/MC.yaml#

# Semantic versions within the model
versions:
- version: "1.0.0"
# Semantic versions within the model
versions:
- version: "1.0.0"

# XLEN used by rakefile
base: 32
# XLEN used by rakefile
base: 32

revision_history:
- revision: "0.7"
date: 2024-07-29
changes:
- First version after moving non-microcontroller content in this document to a new document
called “RISC-V CRDs (Certification Requirement Documents)”
- Change MC100 Unpriv ISA spec from
“https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
2016” to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
former isn't ratified by the latter is the oldest ratified version.
- Added requirements for WFI instruction
- Added requirements related to msip memory-mapped register
- revision: "0.6"
date: 2024-07-11
changes:
- Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
- Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
- Added a table showing the mapping from MC version to ISA manuals.
- Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller
was ratified at that time and isn’t anticipated to be the interrupt controller used by MC100 implementations.
- Clarified MANDATORY behaviors for mie and mip CSRs
- Removed canonical discovery recipe because the OPT-* options directly inform the certification
tests and certification reference model of the status of the various options. Also, canonical
discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
potentially illegal values to CSR fields.
- Added more options for interrupts
- Moved non-microcontroller content in this document to a new document called “RISC-V Certification Plans”
- revision: "0.5"
date: 2024-06-03
changes:
- Renamed to “RISC-V Microcontroller Certification Plan” based on Jason’s recommendation
- Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
these are mandatory in M-mode v1.13 (probably older versions too, haven’t looked yet).
- Added table showing mapping of MC versions to associated RISC-V specifications
- revision: "0.4"
date: 2024-06-03
changes:
- Added M-mode instruction requirements
- Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
- Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
- revision: "0.3"
date: 2024-05-25
changes:
- Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
- revision: "0.2"
date: 2024-05-20
changes:
- Very early draft
- revision: "0.1"
date: 2024-05-16
changes:
- Initial version
revision_history:
- revision: "0.7.0"
date: 2024-07-29
changes:
- First version after moving non-microcontroller content in this document to a new document
called "RISC-V CRDs (Certification Requirement Documents)"
- Change MC100 Unpriv ISA spec from
"https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
former isn't ratified by the latter is the oldest ratified version.
- Added requirements for WFI instruction
- Added requirements related to msip memory-mapped register
- revision: "0.6.0"
date: 2024-07-11
changes:
- Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
- Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
- Added a table showing the mapping from MC version to ISA manuals.
- Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller
was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations.
- Clarified MANDATORY behaviors for mie and mip CSRs
- Removed canonical discovery recipe because the OPT-* options directly inform the certification
tests and certification reference model of the status of the various options. Also, canonical
discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
potentially illegal values to CSR fields.
- Added more options for interrupts
- Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans"
- revision: "0.5.0"
date: 2024-06-03
changes:
- Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation
- Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet).
- Added table showing mapping of MC versions to associated RISC-V specifications
- revision: "0.4.0"
date: 2024-06-03
changes:
- Added M-mode instruction requirements
- Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
- Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
- revision: "0.3.0"
date: 2024-05-25
changes:
- Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
- revision: "0.2.0"
date: 2024-05-20
changes:
- Very early draft
- revision: "0.1.0"
date: 2024-05-16
changes:
- Initial version

description: |
MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support:
description: |
MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support:
* The Unprivileged ISA is RV32I with a few extensions suitable for a basic microcontroller
* The M-mode features are those listed as mandatory in the associated RISC-V Privileged ISA manual
* The Unprivileged ISA is RV32I with a few extensions suitable for a basic microcontroller
* The M-mode features are those listed as mandatory in the associated RISC-V Privileged ISA manual
Key features not included in MC100 (i.e., OUT OF SCOPE):
Key features not included in MC100 (i.e., OUT OF SCOPE):
* Interrupt Controller (e.g., CLIC, CLINT, PLIC)
* Features for modes other than M-mode
* PMP
* Debug & trace (TBD)
* Interrupt Controller (e.g., CLIC, CLINT, PLIC)
* Features for modes other than M-mode
* PMP
* Debug & trace (TBD)
# Specification versions
tsc_profile: null # None for MC100
unpriv_isa_manual_revision: "20191213"
priv_isa_manual_revision: "20190608-Priv-MSU-Ratified"
debug_manual_revision: "0.13.2"
# Specification versions
tsc_profile: null # None for MC100
unpriv_isa_manual_revision: "20191213"
priv_isa_manual_revision: "20190608-Priv-MSU-Ratified"
debug_manual_revision: "0.13.2"

# XXX - Remove version information since specifying priv/unpriv ISA manual should imply this.
extensions:
I:
version: "~> 2.1"
presence: mandatory
C:
version: "~> 2.2"
presence: mandatory
M:
version: "~> 2.0"
presence: mandatory
Zicsr:
version: "~> 2.0"
presence: mandatory
Zicntr:
version: "~> 2.0"
presence: mandatory
parameters:
TIME_CSR_IMPLEMENTED: {} # Unconstrained
Sm:
version: "~> 1.11.0"
presence: mandatory
parameters:
MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained
ARCH_ID: {} # Unconstrained
IMP_ID: {} # Unconstrained
VENDOR_ID_BANK: {} # Unconstrained
VENDOR_ID_OFFSET: {} # Unconstrained
MISA_CSR_IMPLEMENTED: {} # Unconstrained
MTVAL_WIDTH: {} # Unconstrained
MTVEC_MODES: {} # Unconstrained
PHYS_ADDR_WIDTH: {} # Unconstrained
MISALIGNED_LDST: {} # Unconstrained
MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained
MISALIGNED_SPLIT_STRATEGY:
schema:
const: by_byte
PRECISE_SYNCHRONOUS_EXCEPTIONS:
schema:
const: true
TRAP_ON_ECALL_FROM_M:
schema:
const: true
TRAP_ON_EBREAK:
schema:
const: true
M_MODE_ENDIANESS:
schema:
const: little
XLEN:
schema:
const: 32
extensions:
I:
version: "~> 2.1"
presence: mandatory
C:
version: "~> 2.2"
presence: mandatory
M:
version: "~> 2.0"
presence: mandatory
Zicsr:
version: "~> 2.0"
presence: mandatory
Zicntr:
version: "~> 2.0"
presence: mandatory
parameters:
TIME_CSR_IMPLEMENTED: {} # Unconstrained
Sm:
version: "~> 1.11.0"
presence: mandatory
parameters:
MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained
ARCH_ID: {} # Unconstrained
IMP_ID: {} # Unconstrained
VENDOR_ID_BANK: {} # Unconstrained
VENDOR_ID_OFFSET: {} # Unconstrained
MISA_CSR_IMPLEMENTED: {} # Unconstrained
MTVAL_WIDTH: {} # Unconstrained
MTVEC_MODES: {} # Unconstrained
PHYS_ADDR_WIDTH: {} # Unconstrained
MISALIGNED_LDST: {} # Unconstrained
MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained
MISALIGNED_SPLIT_STRATEGY:
schema:
const: by_byte
PRECISE_SYNCHRONOUS_EXCEPTIONS:
schema:
const: true
TRAP_ON_ECALL_FROM_M:
schema:
const: true
TRAP_ON_EBREAK:
schema:
const: true
M_MODE_ENDIANESS:
schema:
const: little
XLEN:
schema:
const: 32
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