Merge pull request #437 from riscv-software-src/xqci

Xqci 0.6

arch/ext/Zcd.yaml

@@ -0,0 +1,43 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zcd
+long_name: Compressed instructions for double precision floating point
+description: |
+  Zcd is the existing set of compressed double precision floating point loads and stores:
+  `c.fld`, `c.fldsp`, `c.fsd`, `c.fsdsp`.
+
+type: unprivileged
+company:
+  name: RISC-V International
+  url: https://riscv.org
+versions:
+  - version: "1.0.0"
+    state: ratified
+    ratification_date: 2023-04
+    repositories:
+      - url: https://github.com/riscv/riscv-code-size-reduction
+        branch: main
+    contributors:
+      - name: Tariq Kurd
+      - name: Ibrahim Abu Kharmeh
+      - name: Torbjørn Viem Ness
+      - name: Matteo Perotti
+      - name: Nidal Faour
+      - name: Bill Traynor
+      - name: Rafael Sene
+      - name: Xinlong Wu
+      - name: sinan
+      - name: Jeremy Bennett
+      - name: Heda Chen
+      - name: Alasdair Armstrong
+      - name: Graeme Smecher
+      - name: Nicolas Brunie
+      - name: Jiawei
+    requires:
+      allOf:
+        - anyOf:
+          - { name: Zca, version: "= 1.0.0" }
+          - { name: C, version: "= 1.0.0" }
+        - { name: D, version: "~> 2.2.0" }

cfgs/qc_iu/arch_overlay/ext/Xqci.yaml

@@ -136,6 +136,40 @@ versions:
   requires:
     name: Zca
     version: ">= 1.0.0"
+- version: "0.6.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix encoding of qc.c.extu instruction
+    - Fix encoding of qc.swmi instruction
+    - Rename qc.slasat -> qc.shlsat
+    - Rename qc.sllsat -> qc.shlusat
+  implies:
+  - [Xqcia, "0.4.0"]
+  - [Xqciac, "0.2.0"]
+  - [Xqcibi, "0.2.0"]
+  - [Xqcibm, "0.4.0"]
+  - [Xqcicli, "0.2.0"]
+  - [Xqcicm, "0.2.0"]
+  - [Xqcics, "0.2.0"]
+  - [Xqcicsr, "0.2.0"]
+  - [Xqciint, "0.2.0"]
+  - [Xqcilb, "0.2.0"]
+  - [Xqcili, "0.2.0"]
+  - [Xqcilia, "0.2.0"]
+  - [Xqcilo, "0.2.0"]
+  - [Xqcilsm, "0.4.0"]
+  - [Xqcisls, "0.2.0"]
+  requires:
+    name: Zca
+    version: ">= 1.0.0"
 description: |
   The Xqci extension includes a set of instructions that improve RISC-V code density and
   performance in microontrollers. It fills several gaps:
@@ -431,3 +465,4 @@ doc_license:
 company:
   name: Qualcomm Technologies, Inc.
   url: https://qualcomm.com
+conflicts: [D]

cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml

@@ -40,6 +40,19 @@ versions:
     email: [email protected]
   changes:
     - Fix description and functionality of qc.wrapi instruction
+- version: "0.4.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Rename qc.slasat -> qc.shlsat
+    - Rename qc.sllsat -> qc.shlusat
 description: |
   The Xqcia extension includes eleven instructions to perform integer arithmetic.
 

cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml

@@ -47,7 +47,7 @@ versions:
 description: |
   The Xqciac extension includes three instructions to accelerate common
   address calculations.
-
+conflicts: [D]
 doc_license:
   name: Creative Commons Attribution 4.0 International License
   url: https://creativecommons.org/licenses/by/4.0/

cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml

@@ -43,6 +43,19 @@ versions:
   changes:
     - Fix description and functionality of qc.c.extu instruction
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.4.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix encoding for qc.c.extu
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
   include insertion and extraction.

cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml

@@ -40,6 +40,18 @@ versions:
     email: [email protected]
   changes:
     - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions
+- version: "0.4.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix encoding of qc.swmi
 description: |
   The Xqcilsm extension includes six instructions that transfer multiple values
   between registers and memory.

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml

@@ -22,6 +22,7 @@ encoding:
       not: [0, 1, 2, 3, 4]
     - name: rd
       location: 11-7
+      not: 0
 access:
   s: always
   u: always

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml

@@ -8,9 +8,14 @@ description: |
   Increments `rd` by the multiplication of `rs1` and an unsigned immediate
   Instruction encoded in CL instruction format.
 definedBy:
-  anyOf:
-    - Xqci
-    - Xqciac
+  allOf:
+    - not:
+        anyOf:
+          - allOf: [C, D]
+          - Zcd
+    - anyOf:
+        - Xqci
+        - Xqciac
 base: 32
 encoding:
   match: 001-----------10

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml

@@ -8,9 +8,14 @@ description: |
   Move `rs1` to `rd` if `rd` == 0, keep `rd` value otherwise
   Instruction encoded in CL instruction format.
 definedBy:
-  anyOf:
-    - Xqci
-    - Xqcicm
+  allOf:
+    - anyOf:
+        - Xqci
+        - Xqcicm
+    - not:
+        anyOf:
+          - allOf: [C, D]
+          - Zcd
 base: 32
 encoding:
   match: 101011---00---10

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml → cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shlsat.yaml

@@ -2,8 +2,8 @@
 
 $schema: inst_schema.json#
 kind: instruction
-name: qc.slasat
-long_name: Saturating arithmetic left shift
+name: qc.shlsat
+long_name: Saturating signed left shift
 description: |
   Left shift `rs1` by the value of `rs2`, and saturate the signed result.
   The number of words is in `length`.

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml → cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shlusat.yaml

@@ -2,8 +2,8 @@
 
 $schema: inst_schema.json#
 kind: instruction
-name: qc.sllsat
-long_name: Saturating logical left shift
+name: qc.shlusat
+long_name: Saturating unsigned left shift
 description: |
   Left shift `rs1` by the value of `rs2`, and saturate the unsigned result.
   The number of words is in `length`.

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml

@@ -14,7 +14,7 @@ definedBy:
     - Xqcilsm
 base: 32
 encoding:
-  match: 00---------------111-----0101011
+  match: 01---------------111-----0101011
   variables:
     - name: imm
       location: 29-25