syntax and style change

riscv-software-src · Feb 4, 2025 · 38633e9 · 38633e9
1 parent f9550cd
commit 38633e9
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Showing 2 changed files with 3 additions and 19 deletions.
diff --git a/arch/inst/Zicond/czero.eqz.yaml b/arch/inst/Zicond/czero.eqz.yaml
@@ -8,7 +8,7 @@ description: |
   If rs2 contains the value zero, this instruction writes the value zero to rd. Otherwise, this instruction
   copies the contents of rs1 to rd.
   This instruction carries a syntactic dependency from both rs1 and rs2 to rd. Furthermore, if the Zkt
-  extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2..
+  extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2.
 definedBy: Zicond
 assembly: xd, xs1, xs2
 encoding:
@@ -27,15 +27,7 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-  XReg input1 = X[rs1];
-  XReg input2 = X[rs2];
-  XReg output = 0;
-
-  if(input2 != 0) {
-    output = input1;
-  }
-
-  X[rd] = output;
+  X[rd] = (X[rs2] == 0) ? 0 : X[rs1];
 
 sail(): |
   {

diff --git a/arch/inst/Zicond/czero.nez.yaml b/arch/inst/Zicond/czero.nez.yaml
@@ -27,15 +27,7 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-  XReg input1 = X[rs1];
-  XReg input2 = X[rs2];
-  XReg output = 0;
-
-  if(input2 == 0) {
-    output = input1;
-  }
-
-  X[rd] = output;
+  X[rd] = (X[rs2] != 0) ? 0 : X[rs1];
 
 sail(): |
   {