Add manual generator

.github/workflows/pages.yml

@@ -45,10 +45,16 @@ jobs:
       run: ./do gen:html[generic_rv64]
     - name: Generate YARD docs
       run: ./do gen:tool_doc
-    - name: Create _site
-      run: mkdir -p _site
+    - name: Build manual
+      run: ./do gen:html_manual MANUAL_NAME=isa VERSIONS=all
+    - name: Create _site/example_cfg
+      run: mkdir -p _site/example_cfg
+    - name: Create _site/manual
+      run: mkdir -p _site/manual
     - name: Copy cfg html
-      run: cp -R gen/cfg_html_doc/generic_rv64/html _site
+      run: cp -R gen/cfg_html_doc/generic_rv64/html _site/example_cfg
+    - name: Copy manual html
+      run: cp -R gen/manual/top/all/html _site/manual
     - name: Setup Pages
       uses: actions/configure-pages@v5
     - name: Upload artifact

README.adoc

@@ -15,7 +15,7 @@ This repository contains:
 
 === Working examples:
 
- * Generate https://riscv-software-src.github.io/riscv-unified-db/html/index.html[configuration-specific documentation] taylored to the set of implemented extensions and unnamed implementation options (_e.g._, `./do gen:html[generic_rv64]`).
+ * Generate https://riscv-software-src.github.io/riscv-unified-db/manual/index.html[configuration-specific documentation] taylored to the set of implemented extensions and unnamed implementation options (_e.g._, `./do gen:html[generic_rv64]`).
  ** Only implemented extensions/instructions/CSRs are included
  ** Unreachable/unimplmented parts of the formal specification are pruned away
  ** A dedicated documentation page for every implemented instruction, including its encoding, pruned execution behavior, and what types of exceptions it may cause.

arch/ext/A.yaml

@@ -7,16 +7,16 @@ A:
     name: RISC-V International
     url: https://riscv.org
   versions:
-  - version: 2.1
+  - version: "2.1.0"
     state: ratified
     ratification_date: 2019-12
     contributors:
     - name: Unknown
       email: [email protected]
       company: Unknown
     implies:
-    - [Zaamo, 1.0]
-    - [Zalrsc, 1.0]
+    - [Zaamo, "1.0.0"]
+    - [Zalrsc, "1.0.0"]
   description: |
 
     The atomic-instruction extension, named `A`, contains

arch/ext/B.yaml

@@ -10,7 +10,7 @@ B:
     name: Creative Commons Attribution 4.0 International License
     url: https://creativecommons.org/licenses/by/4.0/
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2024-04
     contributors:
@@ -19,9 +19,9 @@ B:
       company: Rivos, Inc.
     url: https://drive.google.com/file/d/1SgLoasaBjs5WboQMaU3wpHkjUwV71UZn/view
     implies:
-    - [Zba, 1.0]
-    - [Zbb, 1.0]
-    - [Zbs, 1.0]
+    - [Zba, "1.0.0"]
+    - [Zbb, "1.0.0"]
+    - [Zbs, "1.0.0"]
   description: |
     The B standard extension comprises instructions provided by the `Zba`, `Zbb`, and `Zbs` extensions.
 

arch/ext/C.yaml

@@ -4,7 +4,7 @@ C:
   type: unprivileged
   long_name: Compressed instructions
   versions:
-  - version: 2.2
+  - version: "2.2.0"
     state: ratified
     ratification_date: 2019-12
   description: |

arch/ext/D.yaml

@@ -4,12 +4,12 @@ D:
   type: unprivileged
   long_name: Double-precision floating-point
   versions:
-  - version: 2.2
+  - version: "2.2.0"
     state: ratified
     ratification_date: 2019-12
     changes:
     - Define NaN-boxing scheme, changed definition of FMAX and FMIN
-    implies: [F, 2.2]
+    implies: [F, "2.2.0"]
   description: |
     The `D` extension adds
     double-precision floating-point computational instructions compliant

arch/ext/F.yaml

@@ -4,7 +4,7 @@ F:
   type: unprivileged
   long_name: Single-precision floating-point
   versions:
-  - version: 2.2
+  - version: "2.2.0"
     state: ratified
     ratification_date: 2019-12
     changes:

arch/ext/H.yaml

@@ -4,12 +4,12 @@ H:
   type: privileged
   long_name: Hypervisor
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2019-12
     requires:
       oneOf:
-      - [S, '>= 1.12']
+      - [S, '>= 1.12.0']
   interrupt_codes:
   - num: 2
     name: Virtual supervisor software interrupt

arch/ext/I.yaml

@@ -4,7 +4,7 @@ I:
   type: unprivileged
   long_name: Base integer ISA
   versions:
-  - version: 2.1
+  - version: "2.1.0"
     state: ratified
     ratification_date: 2019-06
     changes:
@@ -73,6 +73,11 @@ I:
   - num: 15
     name: Store/AMO page fault
     var: StoreAmoPageFault
+  - num: 18
+    name: Software Check
+    var: SoftwareCheck
+    when:
+      version: ">= 2.1.0"
   params:
     XLEN:
       description: |

arch/ext/M.yaml

@@ -4,7 +4,7 @@ M:
   type: unprivileged
   long_name: Integer multiply and divide instructions
   versions:
-  - version: 2.0
+  - version: "2.0.0"
     state: ratified
     ratification_date: 2019-12
   description: |

arch/ext/S.yaml

@@ -4,10 +4,10 @@ S:
   type: privileged
   long_name: Supervisor mode
   versions:
-  - version: 1.12
+  - version: "1.12.0"
     state: ratified
     ratification_date: 2019-12
-    requires: [U, "= 1.12"]
+    requires: [U, "= 1.12.0"]
   description: |
     This chapter describes the RISC-V supervisor-level architecture, which
     contains a common core that is used with various supervisor-level

arch/ext/Smaia.yaml

@@ -5,7 +5,7 @@ Smaia:
   description: Advanced Interrupt Architecture, M-mode extension
   type: privileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2023-06
     url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf

arch/ext/Smcdeleg.yaml

@@ -4,8 +4,32 @@ Smcdeleg:
   long_name: Performance counter delegation
   description: Performance counter delegation
   type: privileged
+  rvi_jira_issue: RVS-1005
+  company:
+    name: RISC-V International
+    url: https://riscv.org
+  doc_license:
+    name: Creative Commons Attribution 4.0 International License (CC-BY 4.0)
+    url: https://creativecommons.org/licenses/by/4.0/
   versions:
-  - version: 0
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
-    url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx
+    repositories:
+      - url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg
+    url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/download/v1.0.0/riscv-smcdeleg-ssccfg-v1.0.0.pdf
+    contributors:
+    - name: Beeman Strong
+      email: [email protected]
+      company: Rivos, Inc.
+    - name: Atish Patra
+      email: [email protected]
+      company: Rivos, Inc.
+    - name: Allen Baum
+      email: [email protected]
+      company: Rivos, Inc.
+    - name: Greg Favor
+      email: [email protected]
+      company: Ventana Microsystems
+    - name: John Hauser
+      email: [email protected]

arch/ext/Smcntrpmf.yaml

@@ -5,7 +5,7 @@ Smcntrpmf:
   description: Cycle and Instret Privilege Mode Filtering
   type: privileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2023-08
     url: https://github.com/riscv/riscv-smcntrpmf/releases/download/v1.0_rc4-frozen/riscv-smcntrpmf-v1.0_rc4.pdf

arch/ext/Ssaia.yaml

@@ -5,7 +5,7 @@ Ssaia:
   description: Advanced Interrupt Architecture, S-mode extension
   type: privileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2023-06
     url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf

arch/ext/Ssccfg.yaml

@@ -5,7 +5,7 @@ Ssccfg:
   description: Supervisor-mode counter configuration
   type: privileged
   versions:
-  - version: 0
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
     url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx

arch/ext/Ssccptr.yaml

@@ -9,7 +9,7 @@ Ssccptr:
     This extension was ratified with the RVA20 profiles.
   type: privileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
     url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0

arch/ext/Sscofpmf.yaml

@@ -5,7 +5,7 @@ Sscofpmf:
   description: Counter Overflow and Privilege Mode Filtering
   type: privileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2023-08
     url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link

arch/ext/Sscounterenw.yaml

@@ -9,7 +9,7 @@ Sscounterenw:
     This extension was ratified with the RVA22 profiles.
   type: privileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2023-08
     url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link

arch/ext/Sstc.yaml

@@ -5,7 +5,7 @@ Sstc:
   description: Superivisor mode timer interrupts
   type: privileged
   versions:
-  - version: 0.9
+  - version: "0.9.0"
     state: ratified
     ratification_date: null
     url: https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view?usp=drive_link

arch/ext/Sstvala.yaml

@@ -15,7 +15,7 @@ Sstvala:
     This extension was ratified with the RVA20 profiles.
   type: privileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
     url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0

arch/ext/Sstvecd.yaml

@@ -8,7 +8,7 @@ Sstvecd:
     four-byte-aligned address.
   type: privileged
   versions:
-  - version: "1.0"
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
     url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0

arch/ext/Sv32.yaml

@@ -5,7 +5,7 @@ Sv32:
   description: 32-bit virtual address translation (3 level)
   type: privileged
   versions:
-  - version: 1.12
+  - version: "1.12.0"
     state: ratified
     ratification_date: unknown
     url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf

arch/ext/Sv39.yaml

@@ -5,7 +5,7 @@ Sv39:
   description: 39-bit virtual address translation (3 level)
   type: privileged
   versions:
-  - version: 1.12
+  - version: "1.12.0"
     state: ratified
     ratification_date: unknown
     url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf

arch/ext/Sv48.yaml

@@ -5,7 +5,7 @@ Sv48:
   description: 48-bit virtual address translation (4 level)
   type: privileged
   versions:
-  - version: 1.12
+  - version: "1.12.0"
     state: ratified
     ratification_date: unknown
     url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf

arch/ext/Sv57.yaml

@@ -5,7 +5,7 @@ Sv57:
   description: 57-bit virtual address translation (5 level)
   type: privileged
   versions:
-  - version: 1.12
+  - version: "1.12.0"
     state: ratified
     ratification_date: unknown
     url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf

arch/ext/Svade.yaml

@@ -8,7 +8,7 @@ Svade:
     during a page walk. Rather, encountering a PTE with the A bit clear or the D bit clear when
     an operation is a write will cause a Page Fault.
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2023-11
     url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf

arch/ext/Svadu.yaml

@@ -91,7 +91,7 @@ Svadu:
     is zero, the implementation behaves as though Svadu were not implemented for
     VS-stage address translation.
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2023-11
     url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf

arch/ext/Svbare.yaml

@@ -9,7 +9,7 @@ Svbare:
     [NOTE]
     This extension was ratified as part of the RVA22 profile.
   versions:
-  - version: "1.0"
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
     requires: S

arch/ext/Svinval.yaml

@@ -71,7 +71,7 @@ Svinval:
     `sfence.w.inval` and `sfence.inval.ir` instructions as no-ops.
     --
   versions:
-  - version: "1.0"
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2021-11
     requires: S

arch/ext/Svpbmt.yaml

@@ -10,7 +10,7 @@ Svpbmt:
     This extension was ratified as part of the RVA22 profile.
   type: privileged
   versions:
-  - version: "1.0"
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
     requires: Sv39

arch/ext/U.yaml

@@ -5,7 +5,7 @@ U:
   description: User-level privilege mode
   type: privileged
   versions:
-  - version: 1.12
+  - version: "1.12.0"
     state: ratified
     ratification_date: 2019-12
   params:

arch/ext/Za128rs.yaml

@@ -13,7 +13,7 @@ Za128rs:
     The minimum reservation set size is effectively determined by the size of atomic accesses in
     the A extension.
   versions:
-  - version: "1.0"
+  - version: "1.0.0"
     state: ratified
     ratification_date: null
     param_constraints:

arch/ext/Zaamo.yaml

@@ -4,7 +4,7 @@ Zaamo:
   long_name: Load-acquire/Store-release atomic instructions
   type: unprivileged
   versions:
-  - version: 1.0
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2024-04
   description: |