sort out extensions xrefs

src/cap-description.adoc

@@ -248,7 +248,7 @@ permission.
 | 6   | <<el_perm>>^1^
 | 7   | <<sl_perm>>^1^
 |==============================================================================
-^1^ This permission is only supported if the implementation supports <<section_ext_cheri_levels,{cheri_levels_ext_name}>>.
+^1^ This permission is only supported if the implementation supports <<cheri_levels_ext,{cheri_levels_ext_name}>>.
 
 The <<m_bit>> is only assigned meaning when the
 implementation supports {cheri_default_ext_name} _and_ <<x_perm>> is set.

src/cheri-pte-ext.adoc

@@ -1,4 +1,5 @@
 [#section_sv_cheri]
+[#cheri_pte_ext]
 == "{cheri_pte_ext_name}" Extension for CHERI Page-Based Virtual-Memory Systems
 
 CHERI is a security mechanism that is generally orthogonal to page-based

src/debug-integration.adoc

@@ -181,7 +181,7 @@ If {cheri_default_ext_name} is implemented:
 
 * The <<m_bit>> is reset to {cheri_int_mode_name} ({INT_MODE_VALUE}).
 * The debugger can set the <<m_bit>> to {cheri_cap_mode_name} ({CAP_MODE_VALUE}) by executing <<MODESW_CAP>> from the program buffer.
-** Executing <<MODESW_CAP>> causes subsequent instruction execution from the program buffer, starting from the next instruction, to be executed in {cheri_cap_mode_name}. It also sets the CHERI execution mode to {cheri_cap_mode_name} on future entry into debug mode.
+** Executing <<MODESW_CAP>> causes subsequent instructions execution from the program buffer, starting from the next instruction, to be executed in {cheri_cap_mode_name}. It also sets the CHERI execution mode to {cheri_cap_mode_name} on future entry into debug mode.
 ** Therefore to enable use of a CHERI debugger, a single <<MODESW_CAP>> only needs to be executed once from the program buffer after resetting the core.
 ** The debugger can also execute <<MODESW_INT>> to change the mode back to {cheri_int_mode_name}, which also affects the execution of the next instruction in the program buffer, updates the <<m_bit>> of <<dinfc>> and controls which CHERI execution mode to enter on the next entry into debug mode.
 

src/insns/acperm_32bit.adoc

@@ -68,7 +68,7 @@ The MXLEN=32 additional rules are:
 [#acperm_bit_field]
 include::../img/acperm_bit_field.edn[]
 
-NOTE: The <<el_perm,EL>>, <<sl_perm,SL>> and <<section_cap_level,CL>> fields are only defined if the implementation supports <<section_ext_cheri_levels,{cheri_levels_ext_name}>>.
+NOTE: The <<el_perm,EL>>, <<sl_perm,SL>> and <<section_cap_level,CL>> fields are only defined if the implementation supports <<cheri_levels_ext,{cheri_levels_ext_name}>>.
 
 NOTE: Even though being included here <<section_cap_level,CL>> is not considered an architectural permission.
 

src/introduction.adoc

@@ -81,20 +81,20 @@ This specification is based on publicly available documentation including
 cite:[cheri-v9-spec] and cite:[woodruff2019cheri]. It defines the following
 extensions to support CHERI alongside RISC-V:
 
-{cheri_base_ext_name}:: Introduces key, minimal CHERI concepts and features to
+<<cheri_base_ext,{cheri_base_ext_name}>>:: Introduces key, minimal CHERI concepts and features to
 the RISC-V ISA. The resulting extended ISA is not
 backwards-compatible with RISC-V.
-{cheri_default_ext_name}:: Extends {cheri_base_ext_name} with features to ensure
+<<cheri_default_ext,{cheri_default_ext_name}>>:: Extends {cheri_base_ext_name} with features to ensure
 that the ISA extended with CHERI allows backwards binary compatibility with
 RISC-V.
-{sh4add_ext_name}::   Addition of <<SH4ADD>> and <<SH4ADD_UW>> for RV64 only, as CHERI capabilities are 16 bytes when XLEN=64
-{lr_sc_bh_ext_name}:: Addition of <<LR_B>>, <<LR_H>>, <<SC_B>>, <<SC_H>> for more accurate atomic locking as the memory ranges are restricted by using bounds, therefore precise locking is needed.
-{cheri_pte_ext_name}:: CHERI extension for RISC-V harts supporting page-based
+<<sh4add_ext,{sh4add_ext_name}>>::   Addition of <<SH4ADD>> and <<SH4ADD_UW>> for RV64 only, as CHERI capabilities are 16 bytes when XLEN=64
+<<lr_sc_bh_ext,{lr_sc_bh_ext_name}>>:: Addition of <<LR_B>>, <<LR_H>>, <<SC_B>>, <<SC_H>> for more accurate atomic locking as the memory ranges are restricted by using bounds, therefore precise locking is needed.
+<<cheri_pte_ext,{cheri_pte_ext_name}>>:: CHERI extension for RISC-V harts supporting page-based
 virtual-memory.
-{cheri_levels_ext_name}:: Extension for supporting capability flow control.
-This extension allows limiting storing of capabilities to specific regions and can be used e.g. for safer data sharing between compartments.
-{tid_ext_name}:: Extension for supporting thread identifiers. This extension
+<<tid_ext,{tid_ext_name}>>:: Extension for supporting thread identifiers. This extension
 improves software compartmentalization on CHERI systems.
+<<cheri_levels_ext,{cheri_levels_ext_name}>>:: Extension for supporting capability flow control.
+This extension allows limiting storing of capabilities to specific regions and can be used e.g. for safer data sharing between compartments.
 
 CAUTION: The extension names are provisional and subject to change.
 
@@ -103,13 +103,13 @@ CAUTION: The extension names are provisional and subject to change.
 [options=header,align=center,width="90%",cols="25,23,52"]
 |==============================================================================
 | Extension               | Status    | Comment
-|{cheri_base_ext_name}    | Stable    | This extension is a candidate for freezing
-|{cheri_default_ext_name} | Stable    | This extension is a candidate for freezing
-|{sh4add_ext_name}        | Stable    | This extension is a candidate for freezing
-|{lr_sc_bh_ext_name}      | Stable    | This extension is a candidate for freezing
-|{cheri_pte_ext_name}     | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level
-|{tid_ext_name}           | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level
-|{cheri_levels_ext_name}  | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level
+|<<cheri_base_ext,   {cheri_base_ext_name}>>    | Stable    | This extension is a candidate for freezing
+|<<cheri_default_ext,{cheri_default_ext_name}>> | Stable    | This extension is a candidate for freezing
+|<<sh4add_ext,       {sh4add_ext_name}>>        | Stable    | This extension is a candidate for freezing
+|<<lr_sc_bh_ext,     {lr_sc_bh_ext_name}>>      | Stable    | This extension is a candidate for freezing
+|<<cheri_pte_ext,    {cheri_pte_ext_name}>>     | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level
+|<<tid_ext,          {tid_ext_name}>>           | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level
+|<<cheri_levels_ext, {cheri_levels_ext_name}>>  | Prototype | This extension is a prototype, software is being developed to use it to increase the maturity level
 |==============================================================================
 
 {cheri_base_ext_name} is defined as the base extension which all CHERI RISC-V

src/level-ext.adoc

@@ -1,4 +1,4 @@
-[#section_ext_cheri_levels]
+[#cheri_levels_ext]
 == "{cheri_levels_ext_name}" Extension for Capability Levels
 
 {cheri_levels_ext_name} is an extension to {cheri_base_ext_name} that adds support for associating a level with capabilities and limiting the flow of capabilities to specific memory region subsets.

src/tables.adoc

@@ -1,6 +1,7 @@
 [appendix]
 == Extension summary
 
+[#lr_sc_bh_ext]
 === {lr_sc_bh_ext_name}
 
 {lr_sc_bh_ext_name} is a separate extension independent of CHERI, but is required for CHERI software.
@@ -14,6 +15,7 @@ These instructions are not controlled by the CRE bits in <<mseccfg>>, <<menvcfg>
 include::generated/Zabhlrsc_insns_table_body.adoc[]
 |==============================================================================
 
+[#sh4add_ext]
 === {sh4add_ext_name}
 
 {sh4add_ext_name} is a separate extension independent of CHERI, but improves performance for CHERI code
@@ -28,11 +30,12 @@ These instructions are not controlled by the CRE bits in <<mseccfg>>, <<menvcfg>
 include::generated/Zish4add_insns_table_body.adoc[]
 |==============================================================================
 
+[#cheri_base_ext]
 === {cheri_base_ext_name}
 
 {cheri_base_ext_name} defines the set of instructions supported by a core when in {cheri_cap_mode_name}.
 
-Some instructions depend on the presence of other extensions, as listed in xref:Zcheri_purecap_instruction_extension[xrefstyle=short]
+Some instructions depend on the presence of other extensions, as listed in xref:Zcheri_purecap_instruction_extension[xrefstyle=short].
 
 .{cheri_base_ext_name} instruction extension - Pure {cheri_cap_mode_name} instructions
 [#Zcheri_purecap_instruction_extension]
@@ -41,6 +44,7 @@ Some instructions depend on the presence of other extensions, as listed in xref:
 include::generated/Zcheri_purecap_insns_table_body.adoc[]
 |==============================================================================
 
+[#cheri_default_ext]
 === {cheri_default_ext_name}
 
 {cheri_default_ext_name} defines the set of instructions added by the {cheri_int_mode_name}, in addition to {cheri_base_ext_name}.

src/tid-ext.adoc

@@ -1,3 +1,4 @@
+[#tid_ext]
 == "{tid_ext_name}" Extension for Thread Identification
 
 {tid_ext_name} is an optional extension to the RISC-V base ISA.