apply ACPERM rules in order

[tariqkurd-repo]

fixes #426
fixes #428

[arichardson]

I think this is correct, but I'd like @LawrenceEsswood to have a look as well.

[tariqkurd-repo]

@tomaird @jamie-melling - I can't add you as reviewers but can you check this one?

[arichardson]

This looks good to me now - but I'll wait a bit for other to comment on this before merging.

[tomaird]

If we start with the following perms set: R W C X LM ASR EL, mode=1 (int) (i.e. all bits set except SL), e.g from doing an acperm with cs1 having infinite perms and rs2 being 0xfffffff7

Then apply the new rules:

1 - clear ASR because SL is clear
2 - leave C set
3 - leave C set
4 - leave X set
5 - leave W set (beacuse LM set)
6 - leave X set
7 - leave EL set
8 - leave LM set
9 - leave X set
10 - SL was already clear
11 - ASR was cleared by (1)
12 - leave M bit set (int mode)

So we only cleared ASR.

This leaves us with R W C X LM EL, mode=1 (int) which doesn't have an encoding in RV32

So I think we possibly need a new rule to clear X in this case so we end up in quadrant 3, or remove C+LM+EL to stay in quadrant 1 as Execute + Data RW

[arichardson]

If we start with the following perms set: R W C X LM ASR EL, mode=1 (int) (i.e. all bits set except SL), e.g from doing an acperm with cs1 having infinite perms and rs2 being 0xfffffff7

Then apply the new rules:

1 - clear ASR because SL is clear
2 - leave C set
3 - leave C set
4 - leave X set
5 - leave W set (beacuse LM set)
6 - leave X set
7 - leave EL set
8 - leave LM set
9 - leave X set
10 - SL was already clear
11 - ASR was cleared by (1)
12 - leave M bit set (int mode)

So we only cleared ASR.

This leaves us with R W C X LM EL, mode=1 (int) which doesn't have an encoding in RV32

So I think we possibly need a new rule to clear X in this case so we end up in quadrant 3, or remove C+LM+EL to stay in quadrant 1 as Execute + Data RW

Good catch - I'd keep X in this case so go for your second suggestion. EDIT: after discussing this the better approach is to just remove X.

[tariqkurd-repo]

One thing to consider is what happens if SL is cleared but is in a N/A state, we could just ignore it

[arichardson]

Minor comment otherwise LGTM

[LawrenceEsswood]

I think I agree with Alex on Quads 3/4. The encoding was meant to align certain bits with SL (possibly inverted).