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Minor wording fix for mtvecc vectored check #538

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Feb 17, 2025
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Minor wording fix for mtvecc vectored check #538

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2 changes: 1 addition & 1 deletion src/riscv-integration.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -513,7 +513,7 @@ either check fails.

Additionally, when MODE=Vectored the capability has its tag bit cleared if the
capability address + 4 x HICAUSE is not within the <<section_cap_representable_check>>.
HICAUSE is the largest exception cause value that the implementation can write
HICAUSE is the largest interrupt cause value that the implementation can write
to <<mcause>> or <<scause>>/<<vscause>> when an interrupt is taken.

NOTE: When MODE=Vectored, it is only required that address + 4 x HICAUSE is
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