Add RVV segment load/store instructions

[wangpc-pp]

This is needed by golang (and maybe other languages) porting.

We set nf field explicitly.

[wangpc-pp]

cc @4a6f656c

[sequencer]

See

riscv-opcodes/arg_lut.csv

Line 45 in 07b21cc

"nf", 31, 29

[wangpc-pp]

See

riscv-opcodes/arg_lut.csv

Line 45 in 07b21cc

"nf", 31, 29

I don't get it, what do you mean here? We should remove it from this table?

[sequencer]

nf is already encoded in arg_lut, explicit using them in the table is strange, and may break the backward compatibility.

[wangpc-pp]

nf is already encoded in arg_lut, explicit using them in the table is strange, and may break the backward compatibility.

We can just remove it. Currenly, we don't generate memonics for segment load/store in both Golang/Rust. Yes, it is OK for Chisel and other HDL targets, but it is necessary for software porting.

[sequencer]

I see, adding seg load store instruction explicitly look good to me. If this is merged, we can follow it.

[wangpc-pp]

Ping.

[wangpc-pp]

Ping.

[codecov]

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 94.40%. Comparing base (383cbca) to head (e4db348).
Report is 4 commits behind head on master.

Additional details and impacted files

@@            Coverage Diff             @@
##           master     #271      +/-   ##
==========================================
- Coverage   96.53%   94.40%   -2.14%     
==========================================
  Files          10       10              
  Lines         750      750              
==========================================
- Hits          724      708      -16     
- Misses         26       42      +16     

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