Added support of Smepmp in sail Riscv

doc/Status.md

@@ -19,6 +19,8 @@ The Sail specification currently captures the following ISA features:
 
 - Physical Memory Protection (PMP)
 
+- PMP Enhancements for memory accesses and execution prevention on Machine mode (Smepmp)
+
 For the RVWMO memory consistency model, this Sail ISA semantics is integrated with the RVWMO operational model in [the 
 RMEM tool](https://github.com/rems-project/rmem).
 

model/riscv_csr_map.sail

@@ -132,6 +132,8 @@ mapping clause csr_name_map = 0x342  <-> "mcause"
 mapping clause csr_name_map = 0x343  <-> "mtval"
 mapping clause csr_name_map = 0x344  <-> "mip"
 /* machine protection and translation */
+mapping clause csr_name_map = 0x747  <-> "mseccfg"
+mapping clause csr_name_map = 0x757  <-> "mseccfgh"
 mapping clause csr_name_map = 0x3A0  <-> "pmpcfg0"
 mapping clause csr_name_map = 0x3A1  <-> "pmpcfg1"
 mapping clause csr_name_map = 0x3A2  <-> "pmpcfg2"

model/riscv_insts_zicsr.sail

@@ -105,6 +105,9 @@ function readCSR csr : csreg -> xlenbits = {
     (0x343,  _) => mtval,
     (0x344,  _) => mip.bits(),
 
+    (0x747,  _) => mseccfg.bits(),             // mseccfg
+    (0x757, 32) => mseccfgh,                   // mseccfgh
+
     (0x3A0,  _) => pmpReadCfgReg(0),           // pmpcfg0
     (0x3A1, 32) => pmpReadCfgReg(1),           // pmpcfg1
     (0x3A2,  _) => pmpReadCfgReg(2),           // pmpcfg2
@@ -193,6 +196,8 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
     (0x344,  _) => { mip = legalize_mip(mip, value); Some(mip.bits()) },
 
     // Note: Some(value) returned below is not the legalized value due to locked entries
+    (0x747,  _) => { mseccfg->bits() = mseccfgWrite(mseccfg.bits(), value); Some(mseccfg.bits()) },
+    (0x757, 32) => { Some(mseccfgh) }, // ignore writes for now
     (0x3A0,  _) => { pmpWriteCfgReg(0, value); Some(pmpReadCfgReg(0)) },  // pmpcfg0
     (0x3A1, 32) => { pmpWriteCfgReg(1, value); Some(pmpReadCfgReg(1)) },  // pmpcfg1
     (0x3A2,  _) => { pmpWriteCfgReg(2, value); Some(pmpReadCfgReg(2)) },  // pmpcfg2

model/riscv_pmp_control.sail

@@ -104,15 +104,46 @@ function pmpCheckRWX(ent, acc) = {
   }
 }
 
-// this needs to be called with the effective current privilege.
-val pmpCheckPerms: (Pmpcfg_ent, AccessType(ext_access_type), Privilege) -> bool
+/* this needs to be called with the effective current privilege */
+val pmpCheckPerms: (Pmpcfg_ent, AccessType(ext_access_type), Privilege) -> bool effect {rreg}
 function pmpCheckPerms(ent, acc, priv) = {
-  match priv {
-    Machine => if   pmpLocked(ent)
-               then pmpCheckRWX(ent, acc)
-               else true,
-    _       => pmpCheckRWX(ent, acc)
+  if mseccfg.MML() == 0b1 then {
+    if ent.R() == 0b0 & ent.W() == 0b1 then {
+      if pmpLockBit(ent) then {
+        match acc {
+          Execute(_) => true,
+          Read(_)    => priv == Machine & ent.X() == 0b1,
+           _         => false
+        }
+      }
+      else {
+        match acc {
+          Read(_)   => true,
+          Write(_)  => priv == Machine | ent.X() == 0b1,
+            _       => false
+        }
+      }
+    }
+    else {
+      if ent.R() == 0b1 & ent.W() == 0b1 & ent.X() == 0b1 & pmpLockBit(ent) then {
+        match acc {
+          Read(_) => true,
+            _     => false
+        }
+      }
+    else {
+      if (priv == Machine) == pmpLockBit(ent) then 
+        pmpCheckRWX(ent, acc)
+      else false
+    }}
   }
+  else 
+    match priv {
+      Machine => if pmpLockBit(ent) then 
+                 pmpCheckRWX(ent, acc)
+                 else true,
+        _     => pmpCheckRWX(ent, acc)
+    }
 }
 
 /* matching logic */
@@ -218,8 +249,15 @@ function pmpCheck forall 'n, 'n > 0. (addr: xlenbits, width: atom('n), acc: Acce
     PMP_Success  => true,
     PMP_Fail     => false,
     PMP_Continue => match priv {
-                      Machine => true,
-                      _       => false
+                      Machine => if mseccfg.MMWP() == 0b1             /* Make Read, Write and execute denied by default, if condition meets for M mode */
+                                  then false
+                                 else if mseccfg.MML() == 0b1	then {  /* Make execute denied, if condition meets for M mode */
+		                              match acc {
+				                            Execute(_)  => false,
+      	                            	   _      => true
+			                            }}
+	                               else true,        
+                      _       => false                               /* Make Read, Write and execute denied by default for S/U mode */
                     }
   }}}}}}}}}}}}}}}};
 
@@ -234,6 +272,10 @@ function pmpCheck forall 'n, 'n > 0. (addr: xlenbits, width: atom('n), acc: Acce
 }
 
 function init_pmp() -> unit = {
+  mseccfg->RLB() = 0b0;
+  mseccfg->MML() = 0b0;
+  mseccfg->MMWP() = 0b0;
+  mseccfgh = EXTZ(0b0);
   pmp0cfg  = update_A(pmp0cfg,  pmpAddrMatchType_to_bits(OFF));
   pmp1cfg  = update_A(pmp1cfg,  pmpAddrMatchType_to_bits(OFF));
   pmp2cfg  = update_A(pmp2cfg,  pmpAddrMatchType_to_bits(OFF));

model/riscv_pmp_regs.sail

@@ -100,6 +100,15 @@ bitfield Pmpcfg_ent : bits(8) = {
   R : 0         /* read */
 }
 
+bitfield Mseccfg_ent : xlenbits = {
+  RLB : 2,        /* Rule Locking Bypass */
+  MMWP : 1,       /* Machine Mode Whitelist Policy */
+  MML : 0         /* Machine Mode Lockdown */
+}
+
+register mseccfg  : Mseccfg_ent
+register mseccfgh  : bits(32)
+
 register pmp0cfg  : Pmpcfg_ent
 register pmp1cfg  : Pmpcfg_ent
 register pmp2cfg  : Pmpcfg_ent
@@ -154,15 +163,34 @@ function pmpReadCfgReg(n) = {
 }
 
 /* Helpers to handle locked entries */
+function pmpLockBit(cfg: Pmpcfg_ent) -> bool =
+  cfg.L() == 0b1
+
 function pmpLocked(cfg: Pmpcfg_ent) -> bool =
-   cfg.L() == 0b1
+  (cfg.L() == 0b1) & (mseccfg.RLB() == 0b0)
 
 function pmpTORLocked(cfg: Pmpcfg_ent) -> bool =
-   (cfg.L() == 0b1) & (pmpAddrMatchType_of_bits(cfg.A()) == TOR)
-
+  (cfg.L() == 0b1) & (mseccfg.RLB() == 0b0) & (pmpAddrMatchType_of_bits(cfg.A()) == TOR)
+
+/* Function to check whether executable region can be added or not in accordance to 4b of Smepmp spec */
+function checkExe(cfg: Pmpcfg_ent,v: bits(8)) -> Pmpcfg_ent =
+  if ((mseccfg.MML() == 0b1) & (mseccfg.RLB() == 0b0) & (v[7] == bitone)) then {
+   if ((v[0] == bitzero & v[1] == bitzero & v[2] == bitone) |
+       (v[0] == bitzero & v[1] == bitone  & v[2] == bitzero)|
+       (v[0] == bitzero & v[1] == bitone  & v[2] == bitone) |
+       (v[0] == bitone  & v[1] == bitzero & v[2] == bitone))
+   then cfg                           /* If condition meets configuration remains same which means pmpcfg writes are ignored */
+   else Mk_Pmpcfg_ent(v & 0x9f)         /* Bits 5 and 6 are zero */
+  }
+  else {
+   if (mseccfg.MML() == 0b0) & (v[0] == bitzero) & (v[1] == bitone)
+   then Mk_Pmpcfg_ent(v & 0x9c)       /* Bits 5 and 6 are zero and Bits 0 and 1 are zero because of RW=01 reserved combination */
+   else Mk_Pmpcfg_ent(v & 0x9f)        /* Bits 5 and 6 are zero */
+  }
+
 function pmpWriteCfg(cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent =
-  if pmpLocked(cfg) then cfg
-  else Mk_Pmpcfg_ent(v & 0x9f)  // Bits 5 and 6 are zero.
+  if pmpLocked(cfg) then cfg   /* If locked then configuration is unchanged */
+  else checkExe(cfg,v)
 
 val pmpWriteCfgReg : forall 'n, 0 <= 'n < 4 . (atom('n), xlenbits) -> unit effect {rreg, wreg}
 function pmpWriteCfgReg(n, v) = {
@@ -216,3 +244,15 @@ function pmpWriteAddr(locked: bool, tor_locked: bool, reg: xlenbits, v: xlenbits
   if   sizeof(xlen) == 32
   then { if (locked | tor_locked) then reg else v }
   else { if (locked | tor_locked) then reg else EXTZ(v[53..0]) }
+
+function mseccfgWrite(reg: xlenbits, v: xlenbits) -> xlenbits =   /* to set RLB, need to check PMPCFG_L */
+  if mseccfg.RLB() == 0b0 & v[2] == bitone then {
+   if (pmp0cfg.L() == 0b1 | pmp1cfg.L() == 0b1 | pmp2cfg.L() == 0b1 | pmp3cfg.L() == 0b1 
+      | pmp4cfg.L() == 0b1 | pmp5cfg.L() == 0b1 | pmp6cfg.L() == 0b1 | pmp7cfg.L() == 0b1 
+      | pmp8cfg.L() == 0b1 | pmp9cfg.L() == 0b1 | pmp10cfg.L() == 0b1 | pmp11cfg.L() == 0b1 
+      | pmp12cfg.L() == 0b1 | pmp13cfg.L() == 0b1 | pmp14cfg.L() == 0b1 | pmp15cfg.L() == 0b1) 
+   then reg | (v & EXTZ(0b11))
+   else reg | (v & EXTZ(0b111))
+  }
+  else (reg & EXTZ(0b11)) | (v & EXTZ(0b111))  /* Implements stickiness if once set remains set */
+

model/riscv_sys_control.sail

@@ -98,6 +98,9 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
     0x343 => p == Machine, // mtval
     0x344 => p == Machine, // mip
 
+    0x747 => p == Machine, // mseccfg
+    0x757 => p == Machine & (sizeof(xlen) == 32), // mseccfgh
+
     0x3A0 => p == Machine,                        // pmpcfg0
     0x3A1 => p == Machine & (sizeof(xlen) == 32), // pmpcfg1
     0x3A2 => p == Machine,                        // pmpcfg2