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UefiPayloadPkg: Move FADT check to consumer coode.
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ACPI FADT HW register interface fields are
optional but current UPL common entry code made it
as mandatory which caused compatibility issue on
some platforms.

Solution is to move those FADT HW register fields
check code to consumer code so only ASSERT when
those fields are consumed with error.

Currently only AcpiTimerLib and ResetSystemLib
consuming those register fields so if platforms
configured UPL to different library instances the
FADT HW register fields are not consumed thus will
not cause ASSERT.

Signed-off-by: Chasel Chiu <[email protected]>
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ChaselChiu authored and mergify[bot] committed Sep 16, 2024
1 parent 7843c8d commit 670e263
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Showing 3 changed files with 7 additions and 9 deletions.
1 change: 1 addition & 0 deletions UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@ AcpiTimerLibConstructor (
pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);

mPmTimerReg = (UINTN)pAcpiBoardInfo->PmTimerRegBase;
ASSERT (pAcpiBoardInfo->PmTimerRegBase != 0);

return EFI_SUCCESS;
}
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6 changes: 6 additions & 0 deletions UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,12 @@ ResetSystemLibConstructor (
AcpiBoardInfoPtr = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
CopyMem (&mAcpiBoardInfo, AcpiBoardInfoPtr, sizeof (ACPI_BOARD_INFO));

ASSERT (mAcpiBoardInfo.ResetRegAddress != 0);
ASSERT (mAcpiBoardInfo.ResetValue != 0);
ASSERT (mAcpiBoardInfo.PmGpeEnBase != 0);
ASSERT (mAcpiBoardInfo.PmEvtBase != 0);
ASSERT (mAcpiBoardInfo.PmCtrlRegBase != 0);

return EFI_SUCCESS;
}

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9 changes: 0 additions & 9 deletions UefiPayloadPkg/UefiPayloadEntry/AcpiTable.c
Original file line number Diff line number Diff line change
Expand Up @@ -125,15 +125,6 @@ ParseAcpiInfo (
DEBUG ((DEBUG_INFO, "PcieBaseAddr 0x%lx\n", AcpiBoardInfo->PcieBaseAddress));
DEBUG ((DEBUG_INFO, "PcieBaseSize 0x%lx\n", AcpiBoardInfo->PcieBaseSize));

//
// Verify values for proper operation
//
// ASSERT (Fadt->Pm1aCntBlk != 0);
// ASSERT (Fadt->PmTmrBlk != 0);
// ASSERT (Fadt->ResetReg.Address != 0);
// ASSERT (Fadt->Pm1aEvtBlk != 0);
// ASSERT (Fadt->Gpe0Blk != 0);

return RETURN_SUCCESS;
}

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