Start addressing accelerator build error

see Xilinx/KRS#62

Signed-off-by: Víctor Mayoral Vilches <[email protected]>

.gitignore

@@ -1 +1 @@
-firmware/
+firmware/*sysroot.tar.xz

firmware/device_tree/kernel_default.dtbo.dtsi

@@ -0,0 +1,112 @@
+/dts-v1/;
+
+/ {
+
+	fragment@0 {
+		target = <0xffffffff>;
+
+		__overlay__ {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			firmware-name = ".bin";
+			resets = <0xffffffff 0x74>;
+			phandle = <0x03>;
+		};
+	};
+
+	fragment@1 {
+		target = <0xffffffff>;
+
+		__overlay__ {
+			phandle = <0x04>;
+
+			afi0 {
+				compatible = "xlnx,afi-fpga";
+				config-afi = <0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x04 0x00 0x05 0x00 0x06 0x00 0x07 0x00 0x08 0x00 0x09 0x00 0x0a 0x00 0x0b 0x00 0x0c 0x00 0x0d 0x00 0x0e 0xa00 0x0f 0x00>;
+				phandle = <0x05>;
+			};
+
+			clocking0 {
+				#clock-cells = <0x00>;
+				assigned-clock-rates = <0x5f5dd19>;
+				assigned-clocks = <0xffffffff 0x47>;
+				clock-output-names = "fabric_clk";
+				clocks = <0xffffffff 0x47>;
+				compatible = "xlnx,fclk";
+				phandle = <0x06>;
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <0xffffffff>;
+
+		__overlay__ {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			phandle = <0x07>;
+
+			interrupt-controller@80000000 {
+				#interrupt-cells = <0x02>;
+				clock-names = "s_axi_aclk";
+				clocks = <0x01>;
+				compatible = "xlnx,axi-intc-4.1\0xlnx,xps-intc-1.00.a";
+				interrupt-controller;
+				interrupt-names = "irq";
+				interrupt-parent = <0xffffffff>;
+				interrupts = <0x00 0x59 0x04>;
+				reg = <0x00 0x80000000 0x00 0x10000>;
+				xlnx,kind-of-intr = <0x01>;
+				xlnx,num-intr-inputs = <0x20>;
+				phandle = <0x02>;
+			};
+
+			misc_clk_0 {
+				#clock-cells = <0x00>;
+				clock-frequency = <0xbebba30>;
+				compatible = "fixed-clock";
+				phandle = <0x01>;
+			};
+
+			zyxclmm_drm {
+				compatible = "xlnx,zocl";
+				interrupts-extended = <0x02 0x00 0x04 0x02 0x01 0x04 0x02 0x02 0x04 0x02 0x03 0x04 0x02 0x04 0x04 0x02 0x05 0x04 0x02 0x06 0x04 0x02 0x07 0x04 0x02 0x08 0x04 0x02 0x09 0x04 0x02 0x0a 0x04 0x02 0x0b 0x04 0x02 0x0c 0x04 0x02 0x0d 0x04 0x02 0x0e 0x04 0x02 0x0f 0x04 0x02 0x10 0x04 0x02 0x11 0x04 0x02 0x12 0x04 0x02 0x13 0x04 0x02 0x14 0x04 0x02 0x15 0x04 0x02 0x16 0x04 0x02 0x17 0x04 0x02 0x18 0x04 0x02 0x19 0x04 0x02 0x1a 0x04 0x02 0x1b 0x04 0x02 0x1c 0x04 0x02 0x1d 0x04 0x02 0x1e 0x04 0x02 0x1f 0x04>;
+			};
+		};
+	};
+
+	__symbols__ {
+		overlay0 = "/fragment@0/__overlay__";
+		overlay1 = "/fragment@1/__overlay__";
+		afi0 = "/fragment@1/__overlay__/afi0";
+		clocking0 = "/fragment@1/__overlay__/clocking0";
+		overlay2 = "/fragment@2/__overlay__";
+		axi_intc_0 = "/fragment@2/__overlay__/interrupt-controller@80000000";
+		misc_clk_0 = "/fragment@2/__overlay__/misc_clk_0";
+	};
+
+	__fixups__ {
+		fpga_full = "/fragment@0:target:0";
+		zynqmp_reset = "/fragment@0/__overlay__:resets:0";
+		amba = "/fragment@1:target:0\0/fragment@2:target:0";
+		zynqmp_clk = "/fragment@1/__overlay__/clocking0:assigned-clocks:0\0/fragment@1/__overlay__/clocking0:clocks:0";
+		gic = "/fragment@2/__overlay__/interrupt-controller@80000000:interrupt-parent:0";
+	};
+
+	__local_fixups__ {
+
+		fragment@2 {
+
+			__overlay__ {
+
+				interrupt-controller@80000000 {
+					clocks = <0x00>;
+				};
+
+				zyxclmm_drm {
+					interrupts-extended = <0x00 0x0c 0x18 0x24 0x30 0x3c 0x48 0x54 0x60 0x6c 0x78 0x84 0x90 0x9c 0xa8 0xb4 0xc0 0xcc 0xd8 0xe4 0xf0 0xfc 0x108 0x114 0x120 0x12c 0x138 0x144 0x150 0x15c 0x168 0x174>;
+				};
+			};
+		};
+	};
+};

firmware/shell.json

@@ -0,0 +1,5 @@
+{
+    "shell_type" : "XRT_FLAT",
+    "num_slots": "1"
+}
+