Merge pull request #29 from rsd-devel/add-micro-arch-conf

Add a feature that easily modifies microarchitectural parameters

Processor/Project/Synplify/ver2017-03.prj

@@ -1,11 +1,12 @@
 #--  Synopsys, Inc.
 #--  Version M-2017.03-SP1
-#--  Project file /home/matsuo/workspace/rsd-verification/rsd-vivado/Processor/Project/Synplify/ver2017-03.prj
-#--  Written on Thu Dec 24 15:04:17 2020
+#--  Project file /home/shioya/work/rsd-open/Processor/Project/Synplify/ver2017-03.prj
+#--  Written on Wed Jan 13 02:14:59 2021
 
 
 #project files
 add_file -verilog -vlog_std sysv "../../Src/SynthesisMacros.sv"
+add_file -verilog -vlog_std sysv "../../Src/MicroArchConf.sv"
 add_file -verilog -vlog_std sysv "../../Src/BasicTypes.sv"
 add_file -verilog -vlog_std sysv "../../Src/Memory/MemoryMapTypes.sv"
 add_file -verilog -vlog_std sysv "../../Src/Cache/CacheSystemTypes.sv"

Processor/Src/.vscode/settings.json

@@ -47,6 +47,16 @@
         "cinttypes": "cpp"
     },
     "cSpell.words": [
+        "LREG",
+        "LSCALAR",
+        "LVECTOR",
+        "PREG",
+        "PSCALAR",
+        "PVEC",
+        "PVECTOR",
+        "RISCV",
+        "SIMD",
+        "Wakeup",
         "Committer",
         "Conv",
         "DCSR",
@@ -124,6 +134,7 @@
         "ifdef",
         "ifndef",
         "localparam",
+        "modport",
         "lreg",
         "lscalar",
         "lvector",

Processor/Src/BasicTypes.sv

@@ -1,10 +1,9 @@
 // Copyright 2019- RSD contributors.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 
-
-
 package BasicTypes;
 
+import MicroArchConf::*;
 
 
 localparam TRUE  = 1'b1;
@@ -58,7 +57,7 @@ localparam LSCALAR_NUM_BIT_WIDTH = $clog2( LSCALAR_NUM );
 typedef logic [LSCALAR_NUM_BIT_WIDTH-1:0] LScalarRegNumPath;
 
 // Physical register number width
-localparam PSCALAR_NUM = 64;
+localparam PSCALAR_NUM = CONF_PSCALAR_NUM;
 localparam PSCALAR_NUM_BIT_WIDTH = $clog2( PSCALAR_NUM );
 typedef logic [PSCALAR_NUM_BIT_WIDTH-1:0] PScalarRegNumPath;
 
@@ -106,7 +105,7 @@ typedef struct packed { // PRegNumPath
 //
 
 // Fetch width
-localparam FETCH_WIDTH = 2;
+localparam FETCH_WIDTH = CONF_FETCH_WIDTH;
 localparam FETCH_WIDTH_BIT_SIZE = $clog2( FETCH_WIDTH ); // log2(FETCH_WIDTH)
 typedef logic [ FETCH_WIDTH_BIT_SIZE-1:0 ] FetchLaneIndexPath;
 
@@ -127,41 +126,24 @@ localparam DISPATCH_WIDTH_BIT_SIZE = FETCH_WIDTH_BIT_SIZE; // log2(DISPATCH_WIDT
 typedef logic [ DISPATCH_WIDTH_BIT_SIZE-1:0 ] DispatchLaneIndexPath;
 
 // Issue width
-`ifdef RSD_MARCH_INT_ISSUE_WIDTH
-    localparam INT_ISSUE_WIDTH =`RSD_MARCH_INT_ISSUE_WIDTH;
-`else
-    localparam INT_ISSUE_WIDTH = 2;
-`endif
+localparam INT_ISSUE_WIDTH = CONF_INT_ISSUE_WIDTH;
 localparam INT_ISSUE_WIDTH_BIT_SIZE = 1; // log2(INT_ISSUE_WIDTH)
 typedef logic [ INT_ISSUE_WIDTH_BIT_SIZE-1:0 ] IntIssueLaneIndexPath;
 typedef logic unsigned [ $clog2(INT_ISSUE_WIDTH):0 ] IntIssueLaneCountPath;
 
 localparam MULDIV_ISSUE_WIDTH = 1;
 localparam MULDIV_STAGE_DEPTH = 3;
 
-`ifdef RSD_MARCH_UNIFIED_MULDIV_MEM_PIPE
-localparam COMPLEX_ISSUE_WIDTH = 0;
-localparam COMPLEX_ISSUE_WIDTH_BIT_SIZE = 1; // log2(COMPLEX_ISSUE_WIDTH)
-typedef logic [ COMPLEX_ISSUE_WIDTH_BIT_SIZE-1:0 ] ComplexIssueLaneIndexPath;
-typedef logic unsigned [ $clog2(COMPLEX_ISSUE_WIDTH):0 ] ComplexIssueLaneCountPath;
-`else
-localparam COMPLEX_ISSUE_WIDTH = 1;
+localparam COMPLEX_ISSUE_WIDTH = CONF_COMPLEX_ISSUE_WIDTH;
 localparam COMPLEX_ISSUE_WIDTH_BIT_SIZE = 1; // log2(COMPLEX_ISSUE_WIDTH)
 typedef logic [ COMPLEX_ISSUE_WIDTH_BIT_SIZE-1:0 ] ComplexIssueLaneIndexPath;
 typedef logic unsigned [ $clog2(COMPLEX_ISSUE_WIDTH):0 ] ComplexIssueLaneCountPath;
-`endif
 
-`ifdef RSD_MARCH_UNIFIED_LDST_MEM_PIPE
-    localparam LOAD_ISSUE_WIDTH = 1;
-    localparam STORE_ISSUE_WIDTH = 1;
-    localparam MEM_ISSUE_WIDTH = 1;
-    localparam STORE_ISSUE_LANE_BEGIN = 0;   // Load and store share the same lanes
-`else
-    localparam LOAD_ISSUE_WIDTH = 1;
-    localparam STORE_ISSUE_WIDTH = 1;
-    localparam MEM_ISSUE_WIDTH = 2;
-    localparam STORE_ISSUE_LANE_BEGIN = LOAD_ISSUE_WIDTH;    // Store uses dedicated lanes
-`endif
+localparam LOAD_ISSUE_WIDTH = CONF_LOAD_ISSUE_WIDTH;
+localparam STORE_ISSUE_WIDTH = CONF_STORE_ISSUE_WIDTH;
+localparam MEM_ISSUE_WIDTH = CONF_MEM_ISSUE_WIDTH;
+localparam STORE_ISSUE_LANE_BEGIN = CONF_STORE_ISSUE_LANE_BEGIN;   // Load and store share the same lanes
+
 
 localparam MEM_ISSUE_WIDTH_BIT_SIZE = 1; // log2(MEM_ISSUE_WIDTH)
 typedef logic [ MEM_ISSUE_WIDTH_BIT_SIZE-1:0 ] MemIssueLaneIndexPath;
@@ -173,7 +155,7 @@ typedef logic [ ISSUE_WIDTH_BIT_SIZE-1:0 ] IssueLaneIndexPath;
 typedef logic unsigned [ ISSUE_WIDTH_BIT_SIZE:0 ] IssueLaneCountPath;
 
 // Commit width
-localparam COMMIT_WIDTH = 2;     //must be more than RENAME_WIDTH for recovery
+localparam COMMIT_WIDTH = CONF_COMMIT_WIDTH;     //must be more than RENAME_WIDTH for recovery
 localparam COMMIT_WIDTH_BIT_SIZE = $clog2(COMMIT_WIDTH); // log2(COMMIT_WIDTH)
 typedef logic [ COMMIT_WIDTH_BIT_SIZE-1:0 ] CommitLaneIndexPath;
 typedef logic unsigned [ COMMIT_WIDTH_BIT_SIZE:0 ] CommitLaneCountPath;

Processor/Src/Cache/CacheSystemTypes.sv

@@ -5,6 +5,7 @@
 
 package CacheSystemTypes;
 
+    import MicroArchConf::*;
     import BasicTypes::*;
     import MemoryMapTypes::*;
 
@@ -15,10 +16,10 @@ package CacheSystemTypes;
     // Main cache parameters.
     // The remaining cache parameters must be fixed or calculated by the following
     // parameters.
-    localparam DCACHE_WAY_NUM = 2;           // The number of ways in a single set
-    localparam DCACHE_INDEX_BIT_WIDTH = 9 - $clog2(DCACHE_WAY_NUM);   // The number of index bits
-    localparam DCACHE_LINE_BYTE_NUM = 8;     // Line size
-    localparam MSHR_NUM = 2;                 // The number of MSHR entries.
+    localparam DCACHE_WAY_NUM = CONF_DCACHE_WAY_NUM;                 // The number of ways in a single set
+    localparam DCACHE_INDEX_BIT_WIDTH = CONF_DCACHE_INDEX_BIT_WIDTH; // The number of index bits
+    localparam DCACHE_LINE_BYTE_NUM = CONF_DCACHE_LINE_BYTE_NUM;     // Line size
+    localparam MSHR_NUM = CONF_DCACHE_MSHR_NUM;                      // The number of MSHR entries.
 
     // Index bits
     localparam DCACHE_INDEX_NUM = 1 << DCACHE_INDEX_BIT_WIDTH;
@@ -256,9 +257,9 @@ package CacheSystemTypes;
     // Main cache parameters.
     // The remaining cache parameters must be fixed or calculated by the following
     // parameters.
-    localparam ICACHE_WAY_NUM = 2;           // Way Num
-    localparam ICACHE_INDEX_BIT_WIDTH = 9 - $clog2(ICACHE_WAY_NUM);   // The number of index bits
-    localparam ICACHE_LINE_BYTE_NUM = 8;    // Line size
+    localparam ICACHE_WAY_NUM = CONF_ICACHE_WAY_NUM;           // Way Num
+    localparam ICACHE_INDEX_BIT_WIDTH = CONF_ICACHE_INDEX_BIT_WIDTH;   // The number of index bits
+    localparam ICACHE_LINE_BYTE_NUM = CONF_ICACHE_LINE_BYTE_NUM;    // Line size
 
     // Index bits
     localparam ICACHE_INDEX_NUM = 1 << ICACHE_INDEX_BIT_WIDTH;

Processor/Src/FetchUnit/FetchUnitTypes.sv

@@ -8,14 +8,15 @@
 
 package FetchUnitTypes;
 
+import MicroArchConf::*;
 import BasicTypes::*;
 import MemoryMapTypes::*;
 
 //
 // BTB
 //
 
-localparam BTB_ENTRY_NUM = 1024;
+localparam BTB_ENTRY_NUM = CONF_BTB_ENTRY_NUM;
 
 // Entry: 1(valid)+4(BTB_TAG_WIDTH)+13(BTB_TAG_WIDTH) = 18 bits
 // The width of a block ram is 18bits, thus the sum of these parameters is set to 18 bits.
@@ -86,15 +87,15 @@ endfunction
 // GShare
 //
 
-localparam BRANCH_GLOBAL_HISTORY_BIT_WIDTH = 10;
+localparam BRANCH_GLOBAL_HISTORY_BIT_WIDTH = CONF_BRANCH_GLOBAL_HISTORY_BIT_WIDTH;
 typedef logic [BRANCH_GLOBAL_HISTORY_BIT_WIDTH-1 : 0] BranchGlobalHistoryPath;
 
 
 //
 // PHT
 //
 
-localparam PHT_ENTRY_NUM = 2048;
+localparam PHT_ENTRY_NUM = CONF_PHT_ENTRY_NUM;
 localparam PHT_ENTRY_NUM_BIT_WIDTH = $clog2(PHT_ENTRY_NUM);
 typedef logic [PHT_ENTRY_NUM_BIT_WIDTH-1:0] PHT_IndexPath;
 

Processor/Src/LoadStoreUnit/LoadStoreUnitTypes.sv

@@ -8,6 +8,7 @@
 
 package LoadStoreUnitTypes;
 
+import MicroArchConf::*;
 import BasicTypes::*;
 import MemoryMapTypes::*;
 import CacheSystemTypes::*;
@@ -42,15 +43,15 @@ function automatic PhyAddrPath LSQ_ToFullAddrFromBlockAddr(LSQ_BlockAddrPath blo
 endfunction
 
 // Load queue
-localparam LOAD_QUEUE_ENTRY_NUM = 16;
+localparam LOAD_QUEUE_ENTRY_NUM = CONF_LOAD_QUEUE_ENTRY_NUM;
 localparam LOAD_QUEUE_ENTRY_NUM_BIT_WIDTH = $clog2(LOAD_QUEUE_ENTRY_NUM);
 
 typedef logic [ LOAD_QUEUE_ENTRY_NUM_BIT_WIDTH-1:0 ] LoadQueueIndexPath;
 typedef logic [ LOAD_QUEUE_ENTRY_NUM_BIT_WIDTH:0 ] LoadQueueCountPath;
 typedef logic [ (1<<LOAD_QUEUE_ENTRY_NUM_BIT_WIDTH)-1:0 ] LoadQueueOneHotPath;
 
 // Store queue
-localparam STORE_QUEUE_ENTRY_NUM = 16;
+localparam STORE_QUEUE_ENTRY_NUM = CONF_STORE_QUEUE_ENTRY_NUM;
 localparam STORE_QUEUE_ENTRY_NUM_BIT_WIDTH = $clog2(STORE_QUEUE_ENTRY_NUM);
 
 typedef logic [ STORE_QUEUE_ENTRY_NUM_BIT_WIDTH-1:0 ] StoreQueueIndexPath;

Processor/Src/Makefiles/CoreSources.inc.mk

@@ -15,6 +15,7 @@ RSD_SRC_CFG = \
 # TYPES には型定義を含む package を含んだファイルを指定する．
 # ファイルごとの依存関係に気をつけて，依存先が依存元より前にくるようにならべること．
 TYPES = \
+	MicroArchConf.sv \
 	BasicTypes.sv \
 	Memory/MemoryMapTypes.sv \
 	Cache/CacheSystemTypes.sv \

Processor/Src/MicroArchConf.sv

@@ -0,0 +1,115 @@
+// Copyright 2021- RSD contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+
+
+package MicroArchConf;
+
+// ---- Front-end
+// Fetch width (instructions). This parameter is configurable.
+localparam CONF_FETCH_WIDTH = 2;
+
+// These parameters cannot be changed and currently must be equal to FETCH_WIDTH.
+localparam CONF_DECODE_WIDTH = CONF_FETCH_WIDTH;      // Decode width
+localparam CONF_RENAME_WIDTH = CONF_FETCH_WIDTH;      // Rename width
+localparam CONF_DISPATCH_WIDTH = CONF_FETCH_WIDTH;    // Dispatch width
+
+
+// ---- Commit
+// Commit width (instructions). This parameter is configurable.
+// must be equal or larger than RENAME_WIDTH (FETCH_WIDTH) for recovery
+localparam CONF_COMMIT_WIDTH = 2;     
+
+
+// --- Back-end
+// The number of physical registers
+localparam CONF_PSCALAR_NUM = 64;
+
+// The number of issue-queue entries
+localparam CONF_ISSUE_QUEUE_ENTRY_NUM = 16;
+
+// The number of active-list (ROB: reorder buffer) entries
+localparam CONF_ACTIVE_LIST_ENTRY_NUM = 64;
+
+// The number of replay-queue entries
+localparam CONF_REPLAY_QUEUE_ENTRY_NUM = 20;
+
+// The following macros can be defined from outside this file.
+//  (e.g., CoreSources.mk or SynthesisMacros.sv)
+// * RSD_MARCH_INT_ISSUE_WIDTH=N:       Set integer issue width to N
+// * RSD_MARCH_UNIFIED_MULDIV_MEM_PIPE: Integrate mul/div to a memory pipe
+// * RSD_MARCH_UNIFIED_LDST_MEM_PIPE:   Use unified LS/ST pipeline
+
+// The issue width of integer pipelines.
+// CONF_INT_ISSUE_WIDTH must be 1 or 2
+`ifdef RSD_MARCH_INT_ISSUE_WIDTH
+    localparam CONF_INT_ISSUE_WIDTH =`RSD_MARCH_INT_ISSUE_WIDTH;
+`else
+    localparam CONF_INT_ISSUE_WIDTH = 2;
+`endif
+
+// The issue width of complex pipelines.
+// CONF_COMPLEX_ISSUE_WIDTH must be zero or one and cannot be changed manually.
+`ifdef RSD_MARCH_UNIFIED_MULDIV_MEM_PIPE
+    localparam CONF_COMPLEX_ISSUE_WIDTH = 0;
+`else
+    localparam CONF_COMPLEX_ISSUE_WIDTH = 1;
+`endif
+
+// The issue width of memory pipelines.
+// These parameters cannot be changed manually.
+localparam CONF_LOAD_ISSUE_WIDTH = 1;       // must be 1
+localparam CONF_STORE_ISSUE_WIDTH = 1;      // must be 1
+`ifdef RSD_MARCH_UNIFIED_LDST_MEM_PIPE
+    localparam CONF_MEM_ISSUE_WIDTH = 1;
+    localparam CONF_STORE_ISSUE_LANE_BEGIN = 0;   // Load and store share the same lane
+`else
+    localparam CONF_MEM_ISSUE_WIDTH = 2;
+    localparam CONF_STORE_ISSUE_LANE_BEGIN = CONF_LOAD_ISSUE_WIDTH;    // Store uses a dedicated lane
+`endif
+
+
+// --- Load store unit
+// These parameters must be a power of two.
+localparam CONF_LOAD_QUEUE_ENTRY_NUM = 16;  // The size of a load queue
+localparam CONF_STORE_QUEUE_ENTRY_NUM = 16; // The size of a store queue
+
+// --- Predictors
+// Branch predictor
+localparam CONF_BTB_ENTRY_NUM = 1024;
+localparam CONF_PHT_ENTRY_NUM = 2048;
+localparam CONF_BRANCH_GLOBAL_HISTORY_BIT_WIDTH = 10;   // Global history length for g-share 
+
+// Memory dependency predictor
+localparam CONF_MDT_ENTRY_NUM = 1024;   // The number of prediction table entries.
+
+
+// --- D-cache
+// Total capacity = CONF_DCACHE_WAY_NUM * 2^CONF_DCACHE_INDEX_BIT_WIDTH * CONF_DCACHE_LINE_BYTE_NUM
+// The number of ways in a single set
+// This parameter must be a power of two. 1 is OK.
+localparam CONF_DCACHE_WAY_NUM = 2;
+
+// The number of index bits
+localparam CONF_DCACHE_INDEX_BIT_WIDTH = 9 - $clog2(CONF_DCACHE_WAY_NUM);   
+
+// Line size. This parameter must be a power of two.
+localparam CONF_DCACHE_LINE_BYTE_NUM = 8;     
+
+// The number of MSHR entries.
+localparam CONF_DCACHE_MSHR_NUM = 2;   
+
+
+// --- I-cache
+// The number of ways in a single set
+// This parameter must be a power of two. It must be larger than 1.
+localparam CONF_ICACHE_WAY_NUM = 2;
+
+// The number of index bits
+localparam CONF_ICACHE_INDEX_BIT_WIDTH = 9 - $clog2(CONF_ICACHE_WAY_NUM);
+
+// Line size. This parameter must be a power of two.
+localparam CONF_ICACHE_LINE_BYTE_NUM = 8;    // Line size
+
+
+endpackage : MicroArchConf
+

Processor/Src/Scheduler/ReplayQueue.sv

@@ -22,11 +22,6 @@ module ReplayQueue(
     ControllerIF.ReplayQueue ctrl
 );
 
-    parameter REPLAY_QUEUE_ENTRY_NUM = 20;
-    parameter REPLAY_QUEUE_ENTRY_NUM_BIT_WIDTH = $clog2(REPLAY_QUEUE_ENTRY_NUM);
-    typedef logic [REPLAY_QUEUE_ENTRY_NUM_BIT_WIDTH-1 : 0] ReplayQueueIndexPath;
-    typedef logic [REPLAY_QUEUE_ENTRY_NUM_BIT_WIDTH : 0] ReplayQueueCountPath;
-
     // A maximum replay interval between two entries in ReplayQueue is
     // equal to a maximum latency of all instruction.
     // TODO: modify this when adding an instruction whose latency is larger than