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RISC-V: check cfg (batch 1) #1764

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Apr 6, 2025
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RISC-V: check cfg (batch 1) #1764

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5 changes: 0 additions & 5 deletions crates/std_detect/src/detect/arch/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -104,20 +104,15 @@ features! {
/// RV128I Base Integer Instruction Set

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
without cfg check: true;
/// "Zicsr" Extension for Control and Status Register (CSR) Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
without cfg check: true;
/// "Zicntr" Extension for Base Counters and Timers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
without cfg check: true;
/// "Zihpm" Extension for Hardware Performance Counters

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
without cfg check: true;
/// "Zifencei" Extension for Instruction-Fetch Fence
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
without cfg check: true;
/// "Zihintpause" Extension for Pause Hint

@FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
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