Cheshire (Digilent Genesys2) support

libplatsupport/plat_include/cheshire/platsupport/plat/apb_timer.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <platsupport/timer.h>
+
+#include <utils/util.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/* The input frequence is the CPU frequency which is 50MHz by default */
+#define APB_TIMER_INPUT_FREQ (50*1000*1000)
+#define APB_TIMER_PADDR   0x18000000
+
+/* Multiple timers */
+#define APB_TIMER_DIST      0x10
+#define APB_TIMER_NUM       2
+#define APB_TIMER_BASE(n)   APB_TIMER_DIST * n
+
+#define CMP_WIDTH               32
+#define APB_TIMER_CTRL_ENABLE   BIT(0);
+#define CMP_MASK                MASK(CMP_WIDTH)
+
+/* Timer IRQs */
+#define APB_TIMER_PLIC_BASE     4
+#define APB_TIMER_IRQ_OVF(n)    APB_TIMER_PLIC_BASE + 2*n + 0x0
+#define APB_TIMER_IRQ_CMP(n)    APB_TIMER_PLIC_BASE + 2*n + 0x1
+
+typedef struct {
+    /* vaddr apb_timer is mapped to */
+    void *vaddr;
+} apb_timer_config_t;
+
+typedef struct apb_timer {
+    volatile struct apb_timer_map *apb_timer_map;
+    uint64_t time_h;
+} apb_timer_t;
+
+struct apb_timer_map {
+    uint32_t time;
+    uint32_t ctrl;
+    uint32_t cmp;
+};
+
+int apb_timer_start(apb_timer_t *apb_timer);
+int apb_timer_stop(apb_timer_t *apb_timer);
+uint64_t apb_timer_get_time(apb_timer_t *apb_timer);
+int apb_timer_set_timeout(apb_timer_t *apb_timer, uint64_t ns);
+int apb_timer_init(apb_timer_t *apb_timer, apb_timer_config_t config);

libplatsupport/plat_include/cheshire/platsupport/plat/serial.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+#include <autoconf.h>
+
+enum chardev_id {
+    PS_SERIAL0,
+    /* defaults */
+    PS_SERIAL_DEFAULT = PS_SERIAL0
+};
+
+#define PS_SERIAL_DEFAULT 0
+
+#define DEFAULT_SERIAL_PADDR NULL
+#define DEFAULT_SERIAL_INTERRUPT 0

libplatsupport/src/plat/cheshire/apb_timer.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <stdio.h>
+#include <assert.h>
+#include <errno.h>
+#include <stdlib.h>
+
+#include <utils/util.h>
+
+#include <platsupport/timer.h>
+#include <platsupport/plat/apb_timer.h>
+
+/* Largest timeout that can be programmed */
+#define MAX_TIMEOUT_NS (BIT(31) * (NS_IN_S / APB_TIMER_INPUT_FREQ))
+
+int apb_timer_start(apb_timer_t *apb_timer)
+{
+    apb_timer->apb_timer_map->ctrl |= APB_TIMER_CTRL_ENABLE;
+    return 0;
+}
+
+int apb_timer_stop(apb_timer_t *apb_timer)
+{
+    /* Disable timer. */
+    apb_timer->apb_timer_map->cmp = CMP_MASK;
+    apb_timer->apb_timer_map->ctrl &= ~APB_TIMER_CTRL_ENABLE;
+    apb_timer->apb_timer_map->time = 0;
+
+    return 0;
+}
+
+int apb_timer_set_timeout(apb_timer_t *apb_timer, uint64_t ns)
+{
+    if (ns > MAX_TIMEOUT_NS) {
+        ZF_LOGE("Cannot program a timeout larget than %ld ns", MAX_TIMEOUT_NS);
+        return -1;
+    }
+
+    apb_timer->apb_timer_map->cmp = ns / (NS_IN_S / APB_TIMER_INPUT_FREQ);
+    apb_timer_start(apb_timer);
+
+    return 0;
+}
+
+uint64_t apb_timer_get_time(apb_timer_t *apb_timer)
+{
+    uint64_t ticks = apb_timer->apb_timer_map->time + apb_timer->time_h;
+    return ticks * (NS_IN_S / APB_TIMER_INPUT_FREQ);
+}
+
+int apb_timer_init(apb_timer_t *apb_timer, apb_timer_config_t config)
+{
+    apb_timer->apb_timer_map = (volatile struct apb_timer_map *) config.vaddr;
+    apb_timer->time_h = 0;
+    return 0;
+}

libplatsupport/src/plat/cheshire/chardev.c

@@ -0,0 +1,16 @@
+/*
+ * Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include "../../chardev.h"
+#include "../../common.h"
+#include <utils/util.h>
+
+struct ps_chardevice *
+ps_cdev_init(enum chardev_id id, const ps_io_ops_t *o, struct ps_chardevice *d)
+{
+    return NULL;
+}
+