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1. Lab1-Counter Lab1-Counter Public

   Forked from EIE2-IAC-Labs/Lab1-Counter

   C++

2. Lab2-SigGen Lab2-SigGen Public

   Forked from EIE2-IAC-Labs/Lab2-SigGen

   2nd Lab Instruction - Signal Generation and Capture

   C++

3. Lab3-FSM Lab3-FSM Public

   Forked from EIE2-IAC-Labs/Lab3-FSM

   Lab 3 is all about designing finite state machines

   C++

4. Cache-Controller Cache-Controller Public

   Forked from omega-rg/Cache-Controller

   Two Level Cache Controller implementation in Verilog HDL

   Verilog

5. RV32I-CPU RV32I-CPU Public

   Trying to implement the RV32I ISA in system verilog

6. Information-Processing-Lab Information-Processing-Lab Public

   Forked from Aaron-Zhao123/ELEC50009

   Course material for ELEC50009

   HTML