First laboratory of Integrated Systems Architecture course: Design of an IIR filter This laboratory was about the design of an IIR filter, the design passed through all the phases that leads to the realization of an integrated circuit, from HDL writing and simulation all the way to layout realization.
On this second laboratory we were requested to analyze a floating point multiplier, in particular the Stage2 (significands multiplier), synthethizing it with different methods and different unsigned multipliers of the ones of synopsys to replace the "*" operator. Finally we were requested to implement our own unsigned multiplier using modified booth recording and a dadda tree adder for partial products addition.
The third laboratory was about the design of a simplified RISCV architecture, the processor had to support some basic instructions in order to run some test programs on it. After design, synthesis and floorplan we had to repeat the same with a modified architecture in wich we added a custom instruction that is not present in the ISA in order to execute the same program with a reduced latency.
Reports link: https://drive.google.com/drive/folders/1MBGeU2S6TI66lyxYu73UepeYp5hO15Ic?usp=sharing