linux-iot2050: Re-add support for SR1.0 prueth to the 6.1-cip kernel

This is widely a backport for current under-review upstream patches to re-add SR1.0 prueth support. Signed-off-by: Jan Kiszka <[email protected]>
siemens · Jan 19, 2024 · 024c46a · 024c46a
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diff --git a/...l/linux/files/patches-6.1/0086-net-ti-icssg-config-add-SR1.0-specific-configuration.patch b/...l/linux/files/patches-6.1/0086-net-ti-icssg-config-add-SR1.0-specific-configuration.patch
@@ -0,0 +1,108 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Diogo Ivo <[email protected]>
+Date: Wed, 17 Jan 2024 17:14:56 +0100
+Subject: [PATCH] net: ti: icssg-config: add SR1.0-specific configuration bits
+
+Add required definitions and structures to properly describe
+SR1.0 devices where they differ from SR2.0.
+
+Based on the work of Roger Quadros, Murali Karicheri and
+Grygorii Strashko in TI's 5.10 SDK [1].
+
+[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/?h=ti-linux-5.10.y
+
+Co-developed-by: Jan Kiszka <[email protected]>
+Signed-off-by: Jan Kiszka <[email protected]>
+Signed-off-by: Diogo Ivo <[email protected]>
+---
+ drivers/net/ethernet/ti/icssg/icssg_config.h | 55 ++++++++++++++++++++
+ 1 file changed, 55 insertions(+)
+
+diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.h b/drivers/net/ethernet/ti/icssg/icssg_config.h
+index 43eb0922172a..65539fec5e58 100644
+--- a/drivers/net/ethernet/ti/icssg/icssg_config.h
++++ b/drivers/net/ethernet/ti/icssg/icssg_config.h
+@@ -23,14 +23,23 @@ struct icssg_flow_cfg {
+ #define PRUETH_NAV_SW_DATA_SIZE	16	/* SW related data size */
+ #define PRUETH_MAX_TX_DESC	512
+ #define PRUETH_MAX_RX_DESC	512
++#define PRUETH_MAX_RX_FLOWS_SR1	4	/* excluding default flow */
+ #define PRUETH_MAX_RX_FLOWS	1	/* excluding default flow */
++#define PRUETH_RX_FLOW_DATA_SR1	3       /* highest priority flow */
+ #define PRUETH_RX_FLOW_DATA	0
+
++/* SR1.0 only */
++#define PRUETH_MAX_RX_MGM_DESC		8
++#define PRUETH_MAX_RX_MGM_FLOWS		2	/* excluding default flow */
++#define PRUETH_RX_MGM_FLOW_RESPONSE	0
++#define PRUETH_RX_MGM_FLOW_TIMESTAMP	1
++
+ #define PRUETH_EMAC_BUF_POOL_SIZE	SZ_8K
+ #define PRUETH_EMAC_POOLS_PER_SLICE	24
+ #define PRUETH_EMAC_BUF_POOL_START	8
+ #define PRUETH_NUM_BUF_POOLS	8
+ #define PRUETH_EMAC_RX_CTX_BUF_SIZE	SZ_16K	/* per slice */
++#define MSMC_RAM_SIZE_SR1	(SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */
+ #define MSMC_RAM_SIZE	\
+ 	(2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \
+ 	 PRUETH_EMAC_RX_CTX_BUF_SIZE * 2))
+@@ -94,6 +103,13 @@ enum icssg_port_state_cmd {
+ #define EMAC_ACCEPT_TAG     0xfffe0002
+ #define EMAC_ACCEPT_PRIOR   0xfffc0000
+
++#define PRUETH_NUM_BUF_POOLS_SR1		16
++#define PRUETH_EMAC_BUF_POOL_START_SR1		8
++#define PRUETH_EMAC_BUF_POOL_MIN_SIZE_SR1	128
++#define PRUETH_EMAC_BUF_SIZE_SR1		1536
++#define PRUETH_EMAC_NUM_BUF_SR1			4
++#define PRUETH_EMAC_BUF_POOL_SIZE_SR1	(PRUETH_EMAC_NUM_BUF_SR1 * \
++					 PRUETH_EMAC_BUF_SIZE_SR1)
+ /* Config area lies in DRAM */
+ #define ICSSG_CONFIG_OFFSET	0x0
+
+@@ -101,6 +117,45 @@ enum icssg_port_state_cmd {
+ #define ICSSG_CONFIG_OFFSET_SLICE0   0
+ #define ICSSG_CONFIG_OFFSET_SLICE1   0x8000
+
++struct icssg_config_sr1 {
++	__le32 status;		/* Firmware status */
++	__le32 addr_lo;		/* MSMC Buffer pool base address low. */
++	__le32 addr_hi;		/* MSMC Buffer pool base address high. Must be 0 */
++	__le32 tx_buf_sz[16];	/* Array of buffer pool sizes */
++	__le32 num_tx_threads;	/* Number of active egress threads, 1 to 4 */
++	__le32 tx_rate_lim_en;	/* Bitmask: Egress rate limit en per thread */
++	__le32 rx_flow_id;	/* RX flow id for first rx ring */
++	__le32 rx_mgr_flow_id;	/* RX flow id for the first management ring */
++	__le32 flags;		/* TBD */
++	__le32 n_burst;		/* for debug */
++	__le32 rtu_status;	/* RTU status */
++	__le32 info;		/* reserved */
++	__le32 reserve;
++	__le32 rand_seed;	/* Used for the random number generation at fw */
++} __packed;
++
++/* SR1.0 shutdown command to stop processing at firmware.
++ * Command format : 0x8101ss00. ss - sequence number. Currently not used
++ * by driver.
++ */
++#define ICSSG_SHUTDOWN_CMD		0x81010000
++
++/* SR1.0 pstate speed/duplex command to set speed and duplex settings
++ * in firmware.
++ * Command format : 0x8102ssPN. ss - sequence number: currently not
++ * used by driver, P - port number: For switch, N - Speed/Duplex state
++ * - Possible values of N:
++ * 0x0 - 10Mbps/Half duplex ;
++ * 0x8 - 10Mbps/Full duplex ;
++ * 0x2 - 100Mbps/Half duplex;
++ * 0xa - 100Mbps/Full duplex;
++ * 0xc - 1Gbps/Full duplex;
++ * NOTE: The above are same as bits [3..1](slice 0) or bits [8..6](slice 1) of
++ * RGMII CFG register. So suggested to read the register to populate the command
++ * bits.
++ */
++#define ICSSG_PSTATE_SPEED_DUPLEX_CMD	0x81020000
++
+ #define ICSSG_NUM_NORMAL_PDS	64
+ #define ICSSG_NUM_SPECIAL_PDS	16
+
diff --git a/...l/linux/files/patches-6.1/0087-net-ti-icssg-prueth-add-SR1.0-specific-configuration.patch b/...l/linux/files/patches-6.1/0087-net-ti-icssg-prueth-add-SR1.0-specific-configuration.patch
@@ -0,0 +1,77 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Diogo Ivo <[email protected]>
+Date: Wed, 17 Jan 2024 17:14:57 +0100
+Subject: [PATCH] net: ti: icssg-prueth: add SR1.0-specific configuration bits
+
+Add fields to differentiate between SR1.0 and SR2.0 in the driver
+as well as the structures necessary to program SR1.0.
+
+Based on the work of Roger Quadros in TI's 5.10 SDK [1].
+
+[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/?h=ti-linux-5.10.y
+
+Co-developed-by: Jan Kiszka <[email protected]>
+Signed-off-by: Jan Kiszka <[email protected]>
+Signed-off-by: Diogo Ivo <[email protected]>
+---
+ drivers/net/ethernet/ti/icssg/icssg_prueth.h | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.h b/drivers/net/ethernet/ti/icssg/icssg_prueth.h
+index 8b6d6b497010..1bdd3d301fde 100644
+--- a/drivers/net/ethernet/ti/icssg/icssg_prueth.h
++++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.h
+@@ -127,6 +127,7 @@ struct prueth_rx_chn {
+
+ /* data for each emac port */
+ struct prueth_emac {
++	bool is_sr1;
+ 	bool fw_running;
+ 	struct prueth *prueth;
+ 	struct net_device *ndev;
+@@ -155,6 +156,10 @@ struct prueth_emac {
+ 	int rx_flow_id_base;
+ 	int tx_ch_num;
+
++	/* SR1.0 Management channel */
++	struct prueth_rx_chn rx_mgm_chn;
++	int rx_mgm_flow_id_base;
++
+ 	spinlock_t lock;	/* serialize access */
+
+ 	/* TX HW Timestamping */
+@@ -182,10 +187,12 @@ struct prueth_emac {
+  * struct prueth_pdata - PRUeth platform data
+  * @fdqring_mode: Free desc queue mode
+  * @quirk_10m_link_issue: 10M link detect errata
++ * @is_sr1: device is SR1.0
+  */
+ struct prueth_pdata {
+ 	enum k3_ring_mode fdqring_mode;
+ 	u32	quirk_10m_link_issue:1;
++	u32	is_sr1:1;
+ };
+
+ /**
+@@ -224,6 +231,7 @@ struct prueth {
+ 	struct device_node *eth_node[PRUETH_NUM_MACS];
+ 	struct prueth_emac *emac[PRUETH_NUM_MACS];
+ 	struct net_device *registered_netdevs[PRUETH_NUM_MACS];
++	struct icssg_config_sr1 config[PRUSS_NUM_PRUS];
+ 	struct regmap *miig_rt;
+ 	struct regmap *mii_rt;
+
+@@ -236,6 +244,13 @@ struct prueth {
+ 	struct icss_iep *iep1;
+ };
+
++struct emac_tx_ts_response_sr1 {
++	u32 lo_ts;
++	u32 hi_ts;
++	u32 reserved;
++	u32 cookie;
++};
++
+ struct emac_tx_ts_response {
+ 	u32 reserved[2];
+ 	u32 cookie;
diff --git a/...s-kernel/linux/files/patches-6.1/0088-net-ti-icssg-classifier-Add-support-for-SR1.0.patch b/...s-kernel/linux/files/patches-6.1/0088-net-ti-icssg-classifier-Add-support-for-SR1.0.patch
@@ -0,0 +1,203 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Diogo Ivo <[email protected]>
+Date: Wed, 17 Jan 2024 17:14:58 +0100
+Subject: [PATCH] net: ti: icssg-classifier: Add support for SR1.0
+
+Add the functions to program the SR1.0 packet classifier.
+
+Based on the work of Roger Quadros in TI's 5.10 SDK [1].
+
+[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/?h=ti-linux-5.10.y
+
+Co-developed-by: Jan Kiszka <[email protected]>
+Signed-off-by: Jan Kiszka <[email protected]>
+Signed-off-by: Diogo Ivo <[email protected]>
+---
+ .../net/ethernet/ti/icssg/icssg_classifier.c  | 113 ++++++++++++++++--
+ drivers/net/ethernet/ti/icssg/icssg_prueth.c  |   2 +-
+ drivers/net/ethernet/ti/icssg/icssg_prueth.h  |   6 +-
+ 3 files changed, 110 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/ti/icssg/icssg_classifier.c b/drivers/net/ethernet/ti/icssg/icssg_classifier.c
+index 6df53ab17fbc..d7288eb6c0fd 100644
+--- a/drivers/net/ethernet/ti/icssg/icssg_classifier.c
++++ b/drivers/net/ethernet/ti/icssg/icssg_classifier.c
+@@ -274,6 +274,16 @@ static void rx_class_set_or(struct regmap *miig_rt, int slice, int n,
+ 	regmap_write(miig_rt, offset, data);
+ }
+
++static u32 rx_class_get_or(struct regmap *miig_rt, int slice, int n)
++{
++	u32 offset, val;
++
++	offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN);
++	regmap_read(miig_rt, offset, &val);
++
++	return val;
++}
++
+ void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac)
+ {
+ 	regmap_write(miig_rt, MAC_INTERFACE_0, (u32)(mac[0] | mac[1] << 8 |
+@@ -288,6 +298,26 @@ void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac)
+ 	regmap_write(miig_rt, offs[slice].mac1, (u32)(mac[4] | mac[5] << 8));
+ }
+
++static void icssg_class_ft1_add_mcast(struct regmap *miig_rt, int slice,
++				      int slot, const u8 *addr, const u8 *mask)
++{
++	int i;
++	u32 val;
++
++	WARN(slot >= FT1_NUM_SLOTS, "invalid slot: %d\n", slot);
++
++	rx_class_ft1_set_da(miig_rt, slice, slot, addr);
++	rx_class_ft1_set_da_mask(miig_rt, slice, slot, mask);
++	rx_class_ft1_cfg_set_type(miig_rt, slice, slot, FT1_CFG_TYPE_EQ);
++
++	/* Enable the FT1 slot in OR enable for all classifiers */
++	for (i = 0; i < ICSSG_NUM_CLASSIFIERS_IN_USE; i++) {
++		val = rx_class_get_or(miig_rt, slice, i);
++		val |= RX_CLASS_FT_FT1_MATCH(slot);
++		rx_class_set_or(miig_rt, slice, i, val);
++	}
++}
++
+ /* disable all RX traffic */
+ void icssg_class_disable(struct regmap *miig_rt, int slice)
+ {
+@@ -331,30 +361,95 @@ void icssg_class_disable(struct regmap *miig_rt, int slice)
+ 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);
+ }
+
+-void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti)
++void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti,
++			 bool is_sr1)
+ {
++	int classifiers_in_use = is_sr1 ? ICSSG_NUM_CLASSIFIERS_IN_USE : 1;
+ 	u32 data;
++	int n;
+
+ 	/* defaults */
+ 	icssg_class_disable(miig_rt, slice);
+
+ 	/* Setup Classifier */
+-	/* match on Broadcast or MAC_PRU address */
+-	data = RX_CLASS_FT_BC | RX_CLASS_FT_DA_P;
++	for (n = 0; n < classifiers_in_use; n++) {
++		/* match on Broadcast or MAC_PRU address */
++		data = RX_CLASS_FT_BC | RX_CLASS_FT_DA_P;
+
+-	/* multicast */
+-	if (allmulti)
+-		data |= RX_CLASS_FT_MC;
++		/* multicast */
++		if (allmulti)
++			data |= RX_CLASS_FT_MC;
+
+-	rx_class_set_or(miig_rt, slice, 0, data);
++		rx_class_set_or(miig_rt, slice, n, data);
+
+-	/* set CFG1 for OR_OR_AND for classifier */
+-	rx_class_sel_set_type(miig_rt, slice, 0, RX_CLASS_SEL_TYPE_OR_OR_AND);
++		/* set CFG1 for OR_OR_AND for classifier */
++		rx_class_sel_set_type(miig_rt, slice, n,
++				      RX_CLASS_SEL_TYPE_OR_OR_AND);
++	}
+
+ 	/* clear CFG2 */
+ 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);
+ }
+
++void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice)
++{
++	u32 data, offset;
++	int n;
++
++	/* defaults */
++	icssg_class_disable(miig_rt, slice);
++
++	/* Setup Classifier */
++	for (n = 0; n < ICSSG_NUM_CLASSIFIERS_IN_USE; n++) {
++		/* set RAW_MASK to bypass filters */
++		offset = RX_CLASS_GATES_N_REG(slice, n);
++		regmap_read(miig_rt, offset, &data);
++		data |= RX_CLASS_GATES_RAW_MASK;
++		regmap_write(miig_rt, offset, data);
++	}
++}
++
++void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,
++			       struct net_device *ndev)
++{
++	u8 sr_addr[6] = { 0x01, 0x80, 0xc2, 0, 0, 0 };
++	u8 cb_addr[6] = { 0x01, 0x00, 0x5e, 0, 0, 0 };
++	u8 mask_addr[6] = { 0, 0, 0, 0, 0, 0xff };
++	struct netdev_hw_addr *ha;
++	int slot = 2;
++
++	rx_class_ft1_set_start_len(miig_rt, slice, 0, 6);
++	/* reserve first 2 slots for
++	 *	1) 01-80-C2-00-00-XX Known Service Ethernet Multicast addresses
++	 *	2) 01-00-5e-00-00-XX Local Network Control Block
++	 *			      (224.0.0.0 - 224.0.0.255  (224.0.0/24))
++	 */
++	icssg_class_ft1_add_mcast(miig_rt, slice, 0, sr_addr, mask_addr);
++	icssg_class_ft1_add_mcast(miig_rt, slice, 1, cb_addr, mask_addr);
++	mask_addr[5] = 0;
++	netdev_for_each_mc_addr(ha, ndev) {
++		/* skip addresses matching reserved slots */
++		if (!memcmp(sr_addr, ha->addr, 5) ||
++		    !memcmp(cb_addr, ha->addr, 5)) {
++			netdev_dbg(ndev, "mcast skip %pM\n", ha->addr);
++			continue;
++		}
++
++		if (slot >= FT1_NUM_SLOTS) {
++			netdev_dbg(ndev,
++				   "can't add more than %d MC addresses, enabling allmulti\n",
++				   FT1_NUM_SLOTS);
++			icssg_class_default(miig_rt, slice, 1, true);
++			break;
++		}
++
++		netdev_dbg(ndev, "mcast add %pM\n", ha->addr);
++		icssg_class_ft1_add_mcast(miig_rt, slice, slot,
++					  ha->addr, mask_addr);
++		slot++;
++	}
++}
++
+ /* required for SAV check */
+ void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr)
+ {
+diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/ethernet/ti/icssg/icssg_prueth.c
+index 2b22e98dd677..1f38e115e227 100644
+--- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c
++++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c
+@@ -1329,7 +1329,7 @@ static int emac_ndo_open(struct net_device *ndev)
+ 	icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr);
+ 	icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr);
+
+-	icssg_class_default(prueth->miig_rt, slice, 0);
++	icssg_class_default(prueth->miig_rt, slice, 0, emac->is_sr1);
+
+ 	/* Notify the stack of the actual queue counts. */
+ 	ret = netif_set_real_num_tx_queues(ndev, num_data_chn);
+diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.h b/drivers/net/ethernet/ti/icssg/icssg_prueth.h
+index 1bdd3d301fde..c2221db25950 100644
+--- a/drivers/net/ethernet/ti/icssg/icssg_prueth.h
++++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.h
+@@ -277,7 +277,11 @@ extern const struct ethtool_ops icssg_ethtool_ops;
+ void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac);
+ void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac);
+ void icssg_class_disable(struct regmap *miig_rt, int slice);
+-void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti);
++void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti,
++			 bool is_sr1);
++void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice);
++void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,
++			       struct net_device *ndev);
+ void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr);
+
+ /* config helpers */