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linux-iot2050: Update to v6.1.54-cip6[-rt3]
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This update includes all patches from 5.10 except some prueth functionality
still being upstreamed by TI, namely:

    net: ethernet: ti: icssg_prueth: add TAPRIO offload support
    net: ethernet: ti: icssg_prueth: Add helper functions to configure FDB
    net: ethernet: ti: icssg_switch: Add switchdev based driver for ethernet switch support
    net: ethernet: ti: icssg_prueth: Add support for ICSSG switch firmware on AM654 PG2.0
    ------------------------------- Current upstream attempts stop here--------------------
    net: ethernet: ti: icssg_prueth: add IET Frame preemption utilities
    net: ethernet: ti: icssg_prueth: add priv-flags to configure IET FPE
    net: ethernet: ti: icssg_prueth: enable IET/FPE feature configuration
    net: ethernet: ti: icssg_prueth: Support for transparent ASEL handling
    net: ethernet: ti: icssg_prueth: move phy init in .ndo_open/close()
    net: ethernet: ti: icssg_prueth: fix init after adding switchdev
    net: ti: icssg_prueth: Fix NULL pointer deference during probe
    net: ti: icssg_qos: Remove icssg_qos_cleanup()
    net: ti: icssg_qos: Fix IET Frame Preemption disable path
    net: ti: icssg_prueth: Fix NULL pointer deference during remove
    net: ti: icssg_prueth: Support multiple TX timestamp requests
    net:ti:icssg: select NET_DEVLINK
    net: ethernet: ti: icssg_prueth: Restore half-duplex support
    net: ethernet: ti: icssg_prueth: fix devlink port register sequence
    net: ti: icssg_prueth: clean up pending TX timestamp requests at link down
    net: ti: icssg_prueth: fix missed back to back TX timestamp responses
    net: ti: icssg-prueth: move phy_connect()/phy_disconnect()
    net: ethernet: ti: icssg_prueth: Use page_pool API for RX buffer allocation
    net: ethernet: ti: icssg_prueth: introduce and use prueth_swdata struct for SWDATA
    net: ethernet: ti: icssg_prueth: Add AF_XDP support
    net: ethernet: ti: icssg_prueth: Remove Rx enable in init sequence
    net: ethernet: ti: icssg_prueth: Initialize emac speed on SR1.0

Signed-off-by: Diogo Ivo <[email protected]>
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From 1a37c2908fbcbf95cb3f3e33881a3c11810db513 Mon Sep 17 00:00:00 2001
From: Jan Kiszka <[email protected]>
Date: Thu, 19 Jan 2023 07:40:40 +0100
Subject: [PATCH 01/77] arm64: dts: ti: iot2050: Add layout of OSPI flash

Describe the layout of the OSPI flash as the latest firmware uses it.
Specifically the location of the U-Boot envs is important for userspace
in order to access it.

Signed-off-by: Jan Kiszka <[email protected]>
---
.../boot/dts/ti/k3-am65-iot2050-common.dtsi | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 32b797237581..180bfb2a9ddf 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -603,6 +603,52 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ seboot@0 {
+ label = "seboot";
+ reg = <0x0 0x180000>; /* 1.5M */
+ };
+
+ tispl@180000 {
+ label = "tispl";
+ reg = <0x180000 0x200000>; /* 2M */
+ };
+
+ u-boot@380000 {
+ label = "u-boot";
+ reg = <0x380000 0x300000>; /* 3M */
+ };
+
+ env@680000 {
+ label = "env";
+ reg = <0x680000 0x20000>; /* 128K */
+ };
+
+ env-backup@6a0000 {
+ label = "env.backup";
+ reg = <0x6a0000 0x20000>; /* 128K */
+ };
+
+ otpcmd@6c0000 {
+ label = "otpcmd";
+ reg = <0x6c0000 0x10000>; /* 64K */
+ };
+
+ unused@6d0000 {
+ label = "unused";
+ reg = <0x6d0000 0x7b0000>; /* 7872K */
+ };
+
+ seboot-backup@e80000 {
+ label = "seboot.backup";
+ reg = <0xe80000 0x180000>; /* 1.5M */
+ };
+ };
};
};

--
2.42.0

Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
From c574096089c100319f1447470241cddd05e005e3 Mon Sep 17 00:00:00 2001
From: Jan Kiszka <[email protected]>
Date: Thu, 19 Jan 2023 07:40:41 +0100
Subject: [PATCH 02/77] dt-bindings: arm: ti: Add binding for Siemens IOT2050
M.2 variant

This new variant is derived from the Advanced PG2 board, replacing the
MiniPCI slot with B and E-keyed M.2 slots.

Signed-off-by: Jan Kiszka <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index 28b8232e1c5b..d16231bdee6e 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -42,6 +42,7 @@ properties:
items:
- enum:
- siemens,iot2050-advanced
+ - siemens,iot2050-advanced-m2
- siemens,iot2050-advanced-pg2
- siemens,iot2050-basic
- siemens,iot2050-basic-pg2
--
2.42.0

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@@ -0,0 +1,168 @@
From aac817495c23814a8126ac8bc421b582fe05815c Mon Sep 17 00:00:00 2001
From: chao zeng <[email protected]>
Date: Thu, 19 Jan 2023 07:40:42 +0100
Subject: [PATCH 03/77] arm64: dts: ti: iot2050: Add support for M.2 variant

The M.2 variant comes with 2 slots, one B-keyed and another one E-keyed.
They are configured by the firmware during startup. Also the device tree
will be adjusted according to the detect or manually configured
interface mode by the firmware. The kernel only carries a single
configuration as base device tree. It has to be built with a symbols
node so that the firmware can apply overlays for the connector modes.

Signed-off-by: chao zeng <[email protected]>
[Jan: refactored to a single DT]
Signed-off-by: Jan Kiszka <[email protected]>
Reviewed-by: Siddharth Vadapalli <[email protected]>
---
arch/arm64/boot/dts/ti/Makefile | 3 +
.../dts/ti/k3-am6548-iot2050-advanced-m2.dts | 121 ++++++++++++++++++
2 files changed, 124 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 4555a5be2257..efdd3bb1e263 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -10,8 +10,11 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb

+DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
+
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb

diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
new file mode 100644
index 000000000000..9400e35882a6
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2023
+ *
+ * Authors:
+ * Chao Zeng <[email protected]>
+ * Jan Kiszka <[email protected]>
+ *
+ * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product
+ * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+#include "k3-am6548-iot2050-advanced-common.dtsi"
+#include "k3-am65-iot2050-common-pg2.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-advanced-m2", "ti,am654";
+ model = "SIMATIC IOT2050 Advanced M2";
+};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on this board */
+ ti,cluster-mode = <0>;
+};
+
+&main_pmx0 {
+ main_m2_enable_pins_default: main-m2-enable-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
+ >;
+ };
+
+ main_bkey_pcie_reset: main-bkey-pcie-reset {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
+ >;
+ };
+
+ main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
+ AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
+ >;
+ };
+
+ main_m2_pcie_mux_control: main-m2-pcie-mux-control {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
+ AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
+ AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */
+ >;
+ };
+};
+
+&main_pmx1 {
+ main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
+ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
+ >;
+ };
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &main_m2_pcie_mux_control
+ &arduino_io_d4_to_d9_pins_default
+ >;
+};
+
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &main_m2_enable_pins_default
+ &main_pmx0_m2_config_pins_default
+ &main_pmx1_m2_config_pins_default
+ &cp2102n_reset_pin_default
+ >;
+};
+
+/*
+ * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only.
+ * Firmware switches to other modes via device tree overlays.
+ */
+
+&serdes0 {
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
+};
+
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_bkey_pcie_reset>;
+
+ num-lanes = <2>;
+ phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
+ phy-names = "pcie-phy0","pcie-phy1";
+ reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie1_rc {
+ status = "disabled";
+};
+
+&dwc3_0 {
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
+ /delete-property/ phys;
+ /delete-property/ phy-names;
+};
+
+&usb0 {
+ maximum-speed = "high-speed";
+ /delete-property/ snps,dis-u1-entry-quirk;
+ /delete-property/ snps,dis-u2-entry-quirk;
+};
--
2.42.0

Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
From eff6b753588a19d931f4047dca23e1da85e6d6c0 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <[email protected]>
Date: Mon, 31 May 2021 16:31:35 +0530
Subject: [PATCH 04/77] arm64: dts: ti: k3-am65-main: fix DSS irq trigger type

DSS irq trigger type is set to IRQ_TYPE_EDGE_RISING. For some reason this
results in double the amount of expected interrupts, e.g. for normal
page flipping test the number of interrupts per second is 2 * fps. It is
as if the IRQ would trigger on both edges.

In any case, it's better to use IRQ_TYPE_LEVEL_HIGH, like the other
devices do, which seems to fix this problem.

Signed-off-by: Tomi Valkeinen <[email protected]>
Signed-off-by: Jyri Sarha <[email protected]>
Signed-off-by: Nikhil Devshatwar <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Tested-by: Praneeth Bajjuri <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ebb1c5ce7aec..83dd8993027a 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -856,7 +856,7 @@ dss: dss@4a00000 {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;

- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

dma-coherent;

--
2.42.0

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