uart: speedup, half stopbits support, refactoring

- UART-related tests from sigrok-test now run about ~88% faster.
- Reduced amount of IDLE events by doubling of IDLE period of each frame
  since 3rd. Max IDLE period equals samplerate, thus IDLE events min
  frequency is 1 Hz. This approach decreases function calls up to 10 times
  at idle periods, depends on data sparsity and baudrate selected.
- Calculations of constants in start() to avoid unnecessary overhead
  at runtime.
- Start and end of signal boundaries refined. There is no overlap in
  data bits annotations now. Also packets boundaries are frame boundaries,
  because packet transmission actually starts at start bit and ends with
  stop bit.
- New option put_sample_points added to put sample points at dedicated
  annotation rows with corresponding signal values.
- Options reading moved from runtime to init time for performance,
  a state machine used to control the entire decoding process.
- Support of half stopbit values 0.5 and 1.5.
- Interrupt receiving stop bits on stop bit error and put
  stopbit error in annotation.
- Put data packets to python output.
- Put actual and expected signal at parity error to python output
  instead of dummy tuple.