Merge branch 'master' into refactor_sdfg_list_to_cfg_list

.github/workflows/fpga-ci.yml

@@ -20,20 +20,42 @@ jobs:
       run: |
         rm -f ~/.dace.conf
         rm -rf .dacecache tests/.dacecache
-        . /opt/setupenv
+        python -m venv ~/.venv      # create venv so we can use pip
+        source ~/.venv/bin/activate # activate venv
         python -m pip install --upgrade pip
-        pip install pytest-xdist flake8 coverage
+        pip install pytest-xdist flake8 coverage click
         pip uninstall -y dace
         pip install -e ".[testing]"
         curl -Os https://uploader.codecov.io/latest/linux/codecov
         chmod +x codecov
 
     - name: Run FPGA Tests
       run: |
+        source ~/.venv/bin/activate # activate venv
         export COVERAGE_RCFILE=`pwd`/.coveragerc
+
+        # Xilinx setup
+        export PATH=/opt/Xilinx/Vitis/2022.1/bin:/opt/Xilinx/Vitis_HLS/2022.1/bin:/opt/Xilinx/Vivado/2022.1/bin:$PATH
+        export XILINX_XRT=/opt/xilinx/xrt
+        export LD_LIBRARY_PATH=$XILINX_XRT/lib:$LD_LIBRARY_PATH
+        export XILINX_VITIS=/opt/Xilinx/Vitis/2022.1
+        export DACE_compiler_xilinx_platform=xilinx_u250_gen3x16_xdma_4_1_202210_1
+
+        # Intel FPGA setup
+        export INTELFPGAOCLSDKROOT=/opt/intelFPGA_pro/19.1/hld
+        export ALTERAOCLSDKROOT=$INTELFPGAOCLSDKROOT
+        export AOCL_BOARD_PACKAGE_ROOT=/opt/intelFPGA_pro/19.1/hld/board/a10_ref
+        export PATH=$INTELFPGAOCLSDKROOT/bin:$PATH
+        export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$AOCL_BOARD_PACKAGE_ROOT/linux64/lib
+        export QUARTUS_ROOTDIR_OVERRIDE=/opt/intelFPGA_pro/19.1/quartus
+        export LD_PRELOAD=/lib/x86_64-linux-gnu/libstdc++.so.6   # Work around dependency issues
+
         # Due to an internal bug in the Xilinx tools, where the current datetime is passed as an integer
         # and overflowed in the year 2022, run the FPGA tests pretending like it's January 1st 2021.
-        faketime -f "@2021-01-01 00:00:00" pytest -n auto --cov-report=xml --cov=dace --tb=short -m "fpga"
+        # faketime -f "@2021-01-01 00:00:00" pytest -n auto --cov-report=xml --cov=dace --tb=short -m "fpga"
+        # Try running without faketime
+        pytest -n auto --cov-report=xml --cov=dace --tb=short -m "fpga"
+
         coverage report
         coverage xml
         reachable=0

tests/fpga/jacobi_fpga_test.py

@@ -1,10 +1,12 @@
 # Copyright 2019-2021 ETH Zurich and the DaCe authors. All rights reserved.
 from dace.fpga_testing import xilinx_test, import_sample
 from pathlib import Path
+import pytest
 
 
 # This kernel does not work with the Intel FPGA codegen, because it uses the
 # constant systolic array index in the connector on the nested SDFG.
+@pytest.mark.skip
 @xilinx_test()
 def test_jacobi_fpga():
     jacobi = import_sample(Path("fpga") / "jacobi_fpga_systolic.py")

tests/fpga/map_unroll_processing_elements_test.py

@@ -5,9 +5,11 @@
 import importlib.util
 import numpy as np
 from pathlib import Path
+import pytest
 from dace.config import set_temporary
 
 
+@pytest.mark.skip
 @xilinx_test(assert_ii_1=False)
 def test_map_unroll_processing_elements():
     # Grab the systolic GEMM implementation the samples directory
@@ -54,6 +56,7 @@ def test_map_unroll_processing_elements():
     return sdfg
 
 
+@pytest.mark.skip
 @xilinx_test(assert_ii_1=True)
 def test_map_unroll_processing_elements_decoupled():
     # Grab the systolic GEMM implementation the samples directory

tests/fpga/matmul_test.py

@@ -4,6 +4,7 @@
 import dace.libraries.blas as blas
 from dace.transformation.interstate import FPGATransformSDFG, InlineSDFG
 import numpy as np
+import pytest
 from pathlib import Path
 from dace.config import set_temporary
 
@@ -135,13 +136,13 @@ def test_naive_matmul_fpga():
     return sdfg
 
 
-@fpga_test()
+@fpga_test(xilinx=False)
 def test_systolic_matmul_fpga():
     matmul = import_sample(Path("fpga") / "matrix_multiplication_systolic.py")
     return matmul.run_matmul_systolic(128, 32, 64, 4, False)
 
 
-@fpga_test(assert_ii_1=False)
+@fpga_test(assert_ii_1=False, xilinx=False)
 def test_gemm_vectorized():
     # Test with vectorization
     # To achieve II=1 with Xilinx, we need to decouple reads/writes from memory
@@ -161,6 +162,7 @@ def test_gemm_vectorized():
     return sdfg
 
 
+@pytest.mark.skip
 @xilinx_test(assert_ii_1=True)
 def test_gemm_vectorized_decoupled():
     # Test with vectorization
@@ -181,7 +183,7 @@ def test_gemm_vectorized_decoupled():
     return sdfg
 
 
-@fpga_test(assert_ii_1=False)
+@fpga_test(assert_ii_1=False, xilinx=False)
 def test_gemm_size_not_multiples_of():
 
     # Test with matrix sizes that are not a multiple of #PEs and Tile sizes
@@ -199,6 +201,7 @@ def test_gemm_size_not_multiples_of():
     return sdfg
 
 
+@pytest.mark.skip
 @xilinx_test()
 def test_gemm_size_not_multiples_of_decoupled():
     # Test with matrix sizes that are not a multiple of #PEs and Tile sizes
@@ -218,7 +221,7 @@ def test_gemm_size_not_multiples_of_decoupled():
     return sdfg
 
 
-@fpga_test()
+@fpga_test(xilinx=False)
 def test_matmul_np():
     # Test with numpy matmul, and double precision
     @dace.program
@@ -243,7 +246,7 @@ def matmul_np(A: dace.float64[128, 64], B: dace.float64[64, 32], C: dace.float64
 
 
 if __name__ == "__main__":
-    test_matmul_fpga(None)
+    test_naive_matmul_fpga(None)
     test_systolic_matmul_fpga(None)
     test_gemm_vectorized(None)
     test_gemm_size_not_multiples_of(None)

tests/fpga/reduce_fpga_test.py

@@ -105,7 +105,7 @@ def test_reduce_sum_all_axis():
     return sdfg
 
 
-@fpga_test()
+@fpga_test(xilinx=False)
 def test_reduce_sum_4D():
     A = np.random.rand(4, 4, 4, 12).astype(np.float64)
     B = np.random.rand(4, 4).astype(np.float64)

tests/fpga/simple_systolic_array_test.py

@@ -259,7 +259,7 @@ def make_sdfg(name=None):
     return sdfg
 
 
-@fpga_test()
+@fpga_test(xilinx=False)
 def test_simple_systolic_array():
 
     P.set(4)

tests/fpga/vec_sum_test.py

@@ -8,7 +8,7 @@
 from dace.fpga_testing import fpga_test, xilinx_test
 import numpy as np
 from dace.config import set_temporary
-import argparse
+import pytest
 
 N = dace.symbol("N")
 
@@ -80,6 +80,7 @@ def test_vec_sum_vectorize_first_decoupled_interfaces():
         return run_vec_sum(True)
 
 
+@pytest.mark.skip
 @xilinx_test(assert_ii_1=True)
 def test_vec_sum_fpga_transform_first_decoupled_interfaces():
     # For this test, decoupled read/write interfaces are needed to achieve II=1

tests/npbench/polybench/gemm_npbench_test.py

@@ -85,7 +85,7 @@ def test_gpu():
     run_gemm(dace.dtypes.DeviceType.GPU)
 
 
-@fpga_test(assert_ii_1=False)
+@fpga_test(assert_ii_1=False, xilinx=False)
 def test_fpga():
     return run_gemm(dace.dtypes.DeviceType.FPGA)
 

tests/npbench/polybench/k2mm_test.py

@@ -86,7 +86,7 @@ def test_gpu():
     run_k2mm(dace.dtypes.DeviceType.GPU)
 
 
-@fpga_test(assert_ii_1=False)
+@fpga_test(assert_ii_1=False, xilinx=False)
 def test_fpga():
     return run_k2mm(dace.dtypes.DeviceType.FPGA)
 

tests/npbench/polybench/k3mm_test.py

@@ -82,7 +82,7 @@ def test_gpu():
     run_k3mm(dace.dtypes.DeviceType.GPU)
 
 
-@fpga_test(assert_ii_1=False)
+@fpga_test(assert_ii_1=False, xilinx=False)
 def test_fpga():
     return run_k3mm(dace.dtypes.DeviceType.FPGA)
 

tests/npbench/polybench/lu_test.py

@@ -109,7 +109,7 @@ def test_gpu():
     run_lu(dace.dtypes.DeviceType.GPU)
 
 
-@fpga_test(assert_ii_1=False)
+@fpga_test(assert_ii_1=False, xilinx=False)
 def test_fpga():
     return run_lu(dace.dtypes.DeviceType.FPGA)
 

tests/npbench/polybench/trisolv_test.py

@@ -80,7 +80,7 @@ def test_gpu():
     run_trisolv(dace.dtypes.DeviceType.GPU)
 
 
-@fpga_test(assert_ii_1=False)
+@fpga_test(assert_ii_1=False, xilinx=False)
 def test_fpga():
     return run_trisolv(dace.dtypes.DeviceType.FPGA)