[rtl] add out-of-band signals

stnolting · Dec 27, 2024 · 06ba827 · 06ba827
1 parent b29723c
commit 06ba827
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Showing 5 changed files with 41 additions and 33 deletions.
diff --git a/rtl/core/neorv32_bus.vhd b/rtl/core/neorv32_bus.vhd
@@ -19,8 +19,8 @@ use neorv32.neorv32_package.all;
 
 entity neorv32_bus_switch is
   generic (
-    PORT_A_READ_ONLY : boolean; -- set if port A is read-only
-    PORT_B_READ_ONLY : boolean  -- set if port B is read-only
+    PORT_A_READ_ONLY : boolean := false; -- set if port A is read-only
+    PORT_B_READ_ONLY : boolean := false  -- set if port B is read-only
   );
   port (
     clk_i    : in  std_ulogic; -- global clock, rising edge
@@ -110,20 +110,22 @@ begin
 
   -- Request Switch -------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  x_req_o.addr  <= a_req_i.addr when (arbiter.sel = '0') else b_req_i.addr;
-  x_req_o.rvso  <= a_req_i.rvso when (arbiter.sel = '0') else b_req_i.rvso;
-  x_req_o.priv  <= a_req_i.priv when (arbiter.sel = '0') else b_req_i.priv;
-  x_req_o.src   <= a_req_i.src  when (arbiter.sel = '0') else b_req_i.src;
-  x_req_o.rw    <= a_req_i.rw   when (arbiter.sel = '0') else b_req_i.rw;
-  x_req_o.fence <= a_req_i.fence or b_req_i.fence; -- propagate any fence operations
-
-  x_req_o.data  <= b_req_i.data when PORT_A_READ_ONLY    else
-                   a_req_i.data when PORT_B_READ_ONLY    else
-                   a_req_i.data when (arbiter.sel = '0') else b_req_i.data;
-
-  x_req_o.ben   <= b_req_i.ben  when PORT_A_READ_ONLY    else
-                   a_req_i.ben  when PORT_B_READ_ONLY    else
-                   a_req_i.ben  when (arbiter.sel = '0') else b_req_i.ben;
+  x_req_o.addr  <= a_req_i.addr  when (arbiter.sel = '0') else b_req_i.addr;
+  x_req_o.rvso  <= a_req_i.rvso  when (arbiter.sel = '0') else b_req_i.rvso;
+  x_req_o.priv  <= a_req_i.priv  when (arbiter.sel = '0') else b_req_i.priv;
+  x_req_o.src   <= a_req_i.src   when (arbiter.sel = '0') else b_req_i.src;
+  x_req_o.rw    <= a_req_i.rw    when (arbiter.sel = '0') else b_req_i.rw;
+  x_req_o.fence <= a_req_i.fence or  b_req_i.fence; -- propagate any fence operations
+  x_req_o.sleep <= a_req_i.sleep and b_req_i.sleep; -- set if ALL upstream devices are in sleep mode
+  x_req_o.debug <= a_req_i.debug when (arbiter.sel = '0') else b_req_i.debug;
+
+  x_req_o.data  <= b_req_i.data  when PORT_A_READ_ONLY    else
+                   a_req_i.data  when PORT_B_READ_ONLY    else
+                   a_req_i.data  when (arbiter.sel = '0') else b_req_i.data;
+
+  x_req_o.ben   <= b_req_i.ben   when PORT_A_READ_ONLY    else
+                   a_req_i.ben   when PORT_B_READ_ONLY    else
+                   a_req_i.ben   when (arbiter.sel = '0') else b_req_i.ben;
 
   x_req_o.stb   <= arbiter.stb;
 
@@ -703,10 +705,10 @@ entity neorv32_bus_reservation_set is
     rvs_addr_o  : out std_ulogic_vector(31 downto 0);
     rvs_valid_o : out std_ulogic;
     rvs_clear_i : in  std_ulogic;
-    -- core/cpu port --
+    -- core port --
     core_req_i  : in  bus_req_t;
     core_rsp_o  : out bus_rsp_t;
-    -- system ports --
+    -- system port --
     sys_req_o   : out bus_req_t;
     sys_rsp_i   : in  bus_rsp_t
   );

diff --git a/rtl/core/neorv32_cache.vhd b/rtl/core/neorv32_cache.vhd
@@ -183,7 +183,7 @@ begin
   -- request splitter: cached or direct access --
   req_splitter: process(host_req_i, dir_acc_d)
   begin
-    -- default: pass-through of all bus signals --
+    -- default: pass-through all bus signals --
     cache_req <= host_req_i;
     dir_req_d <= host_req_i;
     -- direct access --
@@ -826,7 +826,7 @@ begin
 
   -- Control Engine FSM Comb ----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  ctrl_engine_comb: process(state, upret, addr, haddr, baddr, bus_rsp_i, cmd_sync_i, cmd_miss_i, rdata_i, dirty_i)
+  ctrl_engine_comb: process(state, upret, addr, haddr, baddr, host_req_i, bus_rsp_i, cmd_sync_i, cmd_miss_i, rdata_i, dirty_i)
   begin
     -- control engine defaults --
     state_nxt <= state;
@@ -845,13 +845,19 @@ begin
     new_o   <= '0';
 
     -- bus interface defaults --
-    bus_req_o      <= req_terminate_c; -- all-zero
-    bus_req_o.addr <= addr.tag & addr.idx & addr.ofs & "00"; -- always word-aligned
-    bus_req_o.data <= rdata_i;
-    bus_req_o.ben  <= (others => '1'); -- full-word writes only
-    bus_req_o.src  <= '0'; -- cache accesses are always "data" accesses
-    bus_req_o.priv <= '0'; -- cache accesses are always "unprivileged" accesses
-    bus_req_o.rvso <= '0'; -- cache accesses can never be a reservation set operation
+    bus_req_o       <= req_terminate_c; -- all-zero
+    bus_req_o.addr  <= addr.tag & addr.idx & addr.ofs & "00"; -- always word-aligned
+    bus_req_o.data  <= rdata_i;
+    bus_req_o.ben   <= (others => '1'); -- full-word writes only
+    bus_req_o.src   <= '0'; -- cache accesses are always data accesses
+    bus_req_o.priv  <= '0'; -- cache accesses are always "unprivileged" accesses
+    bus_req_o.rvso  <= '0'; -- cache accesses can never be a reservation set operation
+    bus_req_o.debug <= host_req_i.debug;
+    if (state = S_IDLE) then
+      bus_req_o.sleep <= host_req_i.sleep;
+    else
+      bus_req_o.sleep <= '0';
+    end if;
 
     -- fsm --
     case state is

diff --git a/rtl/core/neorv32_debug_dm.vhd b/rtl/core/neorv32_debug_dm.vhd
@@ -25,7 +25,6 @@ entity neorv32_debug_dm is
     -- global control --
     clk_i          : in  std_ulogic; -- global clock line
     rstn_i         : in  std_ulogic; -- global reset line, low-active
-    cpu_debug_i    : in  std_ulogic; -- CPU is in debug mode
     -- debug module interface (DMI) --
     dmi_req_i      : in  dmi_req_t; -- request
     dmi_rsp_o      : out dmi_rsp_t; -- response
@@ -69,6 +68,7 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is
   constant addr_progbuf1_c     : std_ulogic_vector(6 downto 0) := "0100001";
   constant addr_authdata_c     : std_ulogic_vector(6 downto 0) := "0110000";
 --constant addr_sbcs_c         : std_ulogic_vector(6 downto 0) := "0111000"; -- hardwired to zero
+  constant addr_haltsum0_c     : std_ulogic_vector(6 downto 0) := "1000000";
 
   -- DMI access --
   signal dmi_wren, dmi_wren_auth, dmi_rden, dmi_rden_auth : std_ulogic;
@@ -666,7 +666,7 @@ begin
   end process bus_access;
 
   -- access helpers --
-  accen <= cpu_debug_i and bus_req_i.stb; -- allow access only when in debug-mode
+  accen <= bus_req_i.debug and bus_req_i.stb; -- allow access only when in debug-mode
   rden  <= accen and (not bus_req_i.rw);
   wren  <= accen and (    bus_req_i.rw);
 

diff --git a/rtl/core/neorv32_dma.vhd b/rtl/core/neorv32_dma.vhd
@@ -310,6 +310,8 @@ begin
   dma_req_o.addr  <= engine.src_addr when (engine.state = S_READ) else engine.dst_addr;
   dma_req_o.rvso  <= '0'; -- no reservation set operation possible
   dma_req_o.fence <= cfg.enable and cfg.fence and engine.done; -- issue FENCE operation when transfer is done
+  dma_req_o.sleep <= '1' when (engine.state = S_IDLE) else '0'; -- idle = sleep mode
+  dma_req_o.debug <= '0'; -- can never ever be in debug mode
 
   -- address increment --
   address_inc: process(cfg.qsel)

diff --git a/rtl/core/neorv32_wdt.vhd b/rtl/core/neorv32_wdt.vhd
@@ -23,8 +23,6 @@ entity neorv32_wdt is
     rstn_sys_i  : in  std_ulogic; -- system reset, low-active
     bus_req_i   : in  bus_req_t;  -- bus request
     bus_rsp_o   : out bus_rsp_t;  -- bus response
-    cpu_debug_i : in  std_ulogic; -- CPU is in debug mode
-    cpu_sleep_i : in  std_ulogic; -- CPU is in sleep mode
     clkgen_en_o : out std_ulogic; -- enable clock generator
     clkgen_i    : in  std_ulogic_vector(7 downto 0);
     rstn_o      : out std_ulogic  -- timeout reset, low_active, sync
@@ -155,8 +153,8 @@ begin
 
   -- valid counter increment? --
   cnt_inc <= '1' when ((prsc_tick = '1') and (cnt_started = '1')) and -- clock tick and started
-                      ((cpu_debug_i = '0') or (ctrl.dben = '1')) and -- not in debug mode or allowed to run in debug mode
-                      ((cpu_sleep_i = '0') or (ctrl.sen = '1')) else '0'; -- not in sleep mode or allowed to run in sleep mode
+                      ((bus_req_i.debug = '0') or (ctrl.dben = '1')) and -- not in debug mode or allowed to run in debug mode
+                      ((bus_req_i.sleep = '0') or (ctrl.sen = '1')) else '0'; -- not in sleep mode or allowed to run in sleep mode
 
   -- timeout detector --
   cnt_timeout <= '1' when (cnt_started = '1') and (cnt = ctrl.timeout) else '0';