[cpu] add page fault exception trigger

yet unused, hardwired to zero

rtl/core/neorv32_cpu.vhd

@@ -206,46 +206,49 @@ begin
   )
   port map (
     -- global control --
-    clk_i         => clk_i,          -- global clock, rising edge
-    clk_aux_i     => clk_aux_i,      -- always-on clock, rising edge
-    rstn_i        => rstn_i,         -- global reset, low-active, async
-    ctrl_o        => ctrl,           -- main control bus
+    clk_i          => clk_i,          -- global clock, rising edge
+    clk_aux_i      => clk_aux_i,      -- always-on clock, rising edge
+    rstn_i         => rstn_i,         -- global reset, low-active, async
+    ctrl_o         => ctrl,           -- main control bus
     -- instruction fetch interface --
-    bus_req_o     => ibus_req_o,     -- request
-    bus_rsp_i     => ibus_rsp_i,     -- response
+    bus_req_o      => ibus_req_o,     -- request
+    bus_rsp_i      => ibus_rsp_i,     -- response
     -- status input --
-    i_pmp_fault_i => pmp_ex_fault,   -- instruction fetch pmp fault
-    alu_cp_done_i => cp_done,        -- ALU iterative operation done
-    lsu_wait_i    => lsu_wait,       -- wait for data bus
-    cmp_i         => alu_cmp,        -- comparator status
+    i_page_fault_i => '0',            -- instruction fetch page fault
+    i_pmp_fault_i  => pmp_ex_fault,   -- instruction fetch pmp fault
+    alu_cp_done_i  => cp_done,        -- ALU iterative operation done
+    lsu_wait_i     => lsu_wait,       -- wait for data bus
+    cmp_i          => alu_cmp,        -- comparator status
     -- data input --
-    alu_add_i     => alu_add,        -- ALU address result
-    rs1_i         => rs1,            -- rf source 1
+    alu_add_i      => alu_add,        -- ALU address result
+    rs1_i          => rs1,            -- rf source 1
     -- data output --
-    imm_o         => imm,            -- immediate
-    fetch_pc_o    => fetch_pc,       -- instruction fetch address
-    curr_pc_o     => curr_pc,        -- current PC (corresponding to current instruction)
-    link_pc_o     => link_pc,        -- link PC (return address)
-    csr_rdata_o   => csr_rdata,      -- CSR read data
+    imm_o          => imm,            -- immediate
+    fetch_pc_o     => fetch_pc,       -- instruction fetch address
+    curr_pc_o      => curr_pc,        -- current PC (corresponding to current instruction)
+    link_pc_o      => link_pc,        -- link PC (return address)
+    csr_rdata_o    => csr_rdata,      -- CSR read data
     -- external CSR interface --
-    xcsr_we_o     => xcsr_we,        -- global write enable
-    xcsr_addr_o   => xcsr_addr,      -- address
-    xcsr_wdata_o  => xcsr_wdata,     -- write data
-    xcsr_rdata_i  => xcsr_rdata_res, -- read data
+    xcsr_we_o      => xcsr_we,        -- global write enable
+    xcsr_addr_o    => xcsr_addr,      -- address
+    xcsr_wdata_o   => xcsr_wdata,     -- write data
+    xcsr_rdata_i   => xcsr_rdata_res, -- read data
     -- debug mode (halt) request --
-    db_halt_req_i => dbi_i,
+    db_halt_req_i  => dbi_i,
     -- interrupts (risc-v compliant) --
-    msi_i         => msi_i,          -- machine software interrupt
-    mei_i         => mei_i,          -- machine external interrupt
-    mti_i         => mti_i,          -- machine timer interrupt
+    msi_i          => msi_i,          -- machine software interrupt
+    mei_i          => mei_i,          -- machine external interrupt
+    mti_i          => mti_i,          -- machine timer interrupt
     -- fast interrupts (custom) --
-    firq_i        => firq_i,         -- fast interrupt trigger
+    firq_i         => firq_i,         -- fast interrupt trigger
     -- bus access exceptions --
-    mar_i         => mar,            -- memory address register
-    ma_load_i     => ma_load,        -- misaligned load data address
-    ma_store_i    => ma_store,       -- misaligned store data address
-    be_load_i     => be_load,        -- bus error on load data access
-    be_store_i    => be_store        -- bus error on store data access
+    mar_i          => mar,            -- memory address register
+    ma_load_i      => ma_load,        -- misaligned load data address
+    ma_store_i     => ma_store,       -- misaligned store data address
+    be_load_i      => be_load,        -- bus error on load data access
+    be_store_i     => be_store,       -- bus error on store data access
+    l_page_fault_i => '0',            -- load page fault
+    s_page_fault_i => '0'             -- store page fault
   );
 
   -- external CSR read-back --