Merge branch 'main' into linty_test

stnolting · Oct 11, 2024 · 3216baf · 3216baf
2 parents 4cd17a5 + 8d978b3
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diff --git a/.github/workflows/Documentation.yml b/.github/workflows/Documentation.yml
@@ -51,11 +51,8 @@ jobs:
       with:
         fetch-depth: 0
 
-    - name: '🐍 Install doit'
-      run: pip install doit
-
     - name: '📚 Build Datasheet and User Guide (PDF and HTML)'
-      run: ./do.py Documentation container
+      run: make -C docs container
 
     - name: '📤 Upload Artifact: HTML'
       uses: actions/upload-artifact@v4
@@ -80,7 +77,7 @@ jobs:
     - name: '📥 Download Artifacts'
       uses: actions/download-artifact@v4
 
-    - name: '🛠️ Organise public subdir and create a tarball'
+    - name: '🛠️ Organize public subdir and create a tarball'
       run: |
         mv NEORV32 public
         mv public/pdf ./
@@ -98,8 +95,15 @@ jobs:
       run: |
         gh release upload nightly NEORV32-SITE-nightly.tar.gz pdf/NEORV32*nightly.pdf --clobber
 
-    - name: '🐍 Install doit'
-      run: pip install doit
-
     - name: '🚀 Deploy to GitHub-Pages'
-      run: ./do.py DeployToGitHubPages "update ${{ github.sha }}"
+      run: |
+        ls -al
+        cd public
+        git init
+        cp ../.git/config ./.git/config
+        touch .nojekyll
+        git add .
+        git config --local user.email "push@gha"
+        git config --local user.name "GHA"
+        git commit -am 'update ${{ github.sha }}'
+        git push -u origin +HEAD:gh-pages
diff --git a/.github/workflows/Processor.yml b/.github/workflows/Processor.yml
@@ -19,16 +19,18 @@ jobs:
 
   Software:
     runs-on: ubuntu-latest
+    container: ghcr.io/stnolting/neorv32/sim
 
     steps:
 
     - name: '🧰 Repository Checkout'
       uses: actions/checkout@v4
 
     - name: '⚙️ Build Software Framework Tests'
-      uses: docker://ghcr.io/stnolting/neorv32/sim
-      with:
-        args: ./do.py SoftwareFrameworkTests
+      run: |
+        make -C sw/example/processor_check check
+        make -C sw/example clean_all exe
+        make -C sw/bootloader clean_all info bootloader
 
 
   Simple:

diff --git a/.gitignore b/.gitignore
@@ -1,9 +1,3 @@
-# doit databases
-/.doit.db.*
-
-# python
-__pycache__
-
 # generated app files
 *.bin
 *.coe

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 11.10.2024 | 1.10.5.5 | :sparkles: :lock: add optional support for on-chip debugger authentication; :warning: rename OCD-related top generics | [#](https://github.com/stnolting/neorv32/pull/1053) |
 | 06.10.2024 | 1.10.5.4 | :warning: rework PWM module | [#1049](https://github.com/stnolting/neorv32/pull/1049) |
 | 05.10.2024 | 1.10.5.3 | upgrade neoTRNG to version 3.2 | [#1048](https://github.com/stnolting/neorv32/pull/1048) |
 | 03.10.2024 | 1.10.5.2 | :warning: remove `A` ISA extensions; replaced by new `Zalrsc` ISA extension | [#1047](https://github.com/stnolting/neorv32/pull/1047) |

diff --git a/README.md b/README.md
@@ -198,6 +198,7 @@ data integrity (CRC8/16/32)
 * compatible to the "Minimal RISC-V Debug Specification Version 1.0"
 * compatible with **OpenOCD**, **GDB** and **Segger Embedded Studio**
 * RISC-V [trigger module](https://stnolting.github.io/neorv32/#_trigger_module) for hardware-assisted breakpoints
+* optional authentication module to implement custom security mechanisms
 
 
 ## 3. FPGA Implementation Results

diff --git a/do.py b/do.py
diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc
@@ -455,8 +455,8 @@ This chapter gives a brief overview of all available ISA extensions.
 | <<_zmmul_isa_extension,`Zmmul`>>       | Integer multiplication-only instructions                      | <<_processor_top_entity_generics, `RISCV_ISA_Zmmul`>>
 | <<_zxcfu_isa_extension,`Zcfu`>>        | Custom / user-defined instructions                            | <<_processor_top_entity_generics, `RISCV_ISA_Zxcfu`>>
 | <<_smpmp_isa_extension,`Smpmp`>>       | Physical memory protection (PMP) extension                    | <<_processor_top_entity_generics, `RISCV_ISA_Smpmp`>>
-| <<_sdext_isa_extension,`Sdext`>>       | External debug support extension                              | <<_processor_top_entity_generics, `ON_CHIP_DEBUGGER_EN`>>
-| <<_sdtrig_isa_extension,`Sdtrig`>>     | Trigger module extension                                      | <<_processor_top_entity_generics, `ON_CHIP_DEBUGGER_EN`>>
+| <<_sdext_isa_extension,`Sdext`>>       | External debug support extension                              | <<_processor_top_entity_generics, `OCD_EN`>>
+| <<_sdtrig_isa_extension,`Sdtrig`>>     | Trigger module extension                                      | <<_processor_top_entity_generics, `OCD_EN`>>
 |=======================
 
 .RISC-V ISA Specification