[cpu] integrate fence signal into CPU bus

- new bus element ".fence" - ⚠️ fence and fence.i instructions behave exactly the same
stnolting · Feb 9, 2024 · 8630587 · 8630587
1 parent 7e7e360
commit 8630587
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Showing 4 changed files with 33 additions and 37 deletions.
diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd
@@ -79,8 +79,6 @@ entity neorv32_cpu is
     rstn_i     : in  std_ulogic; -- global reset, low-active, async
     sleep_o    : out std_ulogic; -- cpu is in sleep mode when set
     debug_o    : out std_ulogic; -- cpu is in debug mode when set
-    ifence_o   : out std_ulogic; -- instruction fence
-    dfence_o   : out std_ulogic; -- data fence
     -- interrupts --
     msi_i      : in  std_ulogic; -- risc-v machine software interrupt
     mei_i      : in  std_ulogic; -- risc-v machine external interrupt
@@ -257,10 +255,6 @@ begin
   sleep_o <= ctrl.cpu_sleep; -- set when CPU is sleeping (after WFI)
   debug_o <= ctrl.cpu_debug; -- set when CPU is in debug mode
 
-  -- instruction/data fence --
-  ifence_o <= ctrl.lsu_fencei;
-  dfence_o <= ctrl.lsu_fence;
-
 
   -- Register File --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------

diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
@@ -432,12 +432,13 @@ begin
   ipb.we(1) <= '1' when (fetch_engine.state = IF_PENDING) and (fetch_engine.resp = '1') else '0';
 
   -- bus access type --
-  bus_req_o.priv <= fetch_engine.priv; -- current effective privilege level
-  bus_req_o.data <= (others => '0'); -- read-only
-  bus_req_o.ben  <= (others => '0'); -- read-only
-  bus_req_o.rw   <= '0'; -- read-only
-  bus_req_o.src  <= '1'; -- source = instruction fetch
-  bus_req_o.rvso <= '0'; -- cannot be a reservation set operation
+  bus_req_o.priv  <= fetch_engine.priv; -- current effective privilege level
+  bus_req_o.data  <= (others => '0'); -- read-only
+  bus_req_o.ben   <= (others => '0'); -- read-only
+  bus_req_o.rw    <= '0'; -- read-only
+  bus_req_o.src   <= '1'; -- source = instruction fetch
+  bus_req_o.rvso  <= '0'; -- cannot be a reservation set operation
+  bus_req_o.fence <= ctrl.lsu_fence; -- fence(.i) operation
 
 
   -- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
@@ -1009,9 +1010,8 @@ begin
         if (trap_ctrl.exc_buf(exc_illegal_c) = '1') then -- abort if illegal instruction
           execute_engine.state_nxt <= DISPATCH;
         else
-          ctrl_nxt.lsu_fence       <= not execute_engine.ir(instr_funct3_lsb_c); -- data fence
-          ctrl_nxt.lsu_fencei      <=     execute_engine.ir(instr_funct3_lsb_c); -- instruction fence
-          execute_engine.state_nxt <= RESTART; -- reset instruction fetch + IPB (only required for fence.i)
+          ctrl_nxt.lsu_fence       <= '1'; -- NOTE: fence == fence.i
+          execute_engine.state_nxt <= RESTART; -- reset instruction fetch + IPB (actually only required for fence.i)
         end if;
 
       when BRANCH => -- update next_PC on taken branches and jumps
@@ -1134,8 +1134,7 @@ begin
   ctrl_o.lsu_req      <= ctrl.lsu_req;
   ctrl_o.lsu_rw       <= ctrl.lsu_rw;
   ctrl_o.lsu_mo_we    <= '1' when (execute_engine.state = MEM_REQ) else '0'; -- write memory output registers (data & address)
-  ctrl_o.lsu_fence    <= ctrl.lsu_fence;
-  ctrl_o.lsu_fencei   <= ctrl.lsu_fencei;
+  ctrl_o.lsu_fence    <= ctrl.lsu_fence; -- fence(.i)
   ctrl_o.lsu_priv     <= csr.mstatus_mpp when (csr.mstatus_mprv = '1') else csr.privilege_eff; -- effective privilege level for loads/stores in M-mode
 
   -- instruction word bit fields --

diff --git a/rtl/core/neorv32_cpu_lsu.vhd b/rtl/core/neorv32_cpu_lsu.vhd
@@ -124,6 +124,9 @@ begin
   -- source identifier --
   bus_req_o.src <= '0'; -- 0 = data access
 
+  -- data/instruction fence(.i)
+  bus_req_o.fence <= ctrl_i.lsu_fence;
+
 
   -- Data Output - Alignment and Byte Enable ------------------------------------------------
   -- -------------------------------------------------------------------------------------------

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -56,7 +56,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090406"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090407"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -152,14 +152,15 @@ package neorv32_package is
   -- -------------------------------------------------------------------------------------------
   -- bus request --
   type bus_req_t is record
-    addr : std_ulogic_vector(31 downto 0); -- access address
-    data : std_ulogic_vector(31 downto 0); -- write data
-    ben  : std_ulogic_vector(03 downto 0); -- byte enable
-    stb  : std_ulogic; -- request strobe (single-shot)
-    rw   : std_ulogic; -- 0=read, 1=write
-    src  : std_ulogic; -- access source (1=instruction fetch, 0=data access)
-    priv : std_ulogic; -- set if privileged (machine-mode) access
-    rvso : std_ulogic; -- set if reservation set operation (atomic LR/SC)
+    addr  : std_ulogic_vector(31 downto 0); -- access address
+    data  : std_ulogic_vector(31 downto 0); -- write data
+    ben   : std_ulogic_vector(03 downto 0); -- byte enable
+    stb   : std_ulogic; -- request strobe (single-shot)
+    rw    : std_ulogic; -- 0=read, 1=write
+    src   : std_ulogic; -- access source (1=instruction fetch, 0=data access)
+    priv  : std_ulogic; -- set if privileged (machine-mode) access
+    rvso  : std_ulogic; -- set if reservation set operation (atomic LR/SC)
+    fence : std_ulogic; -- fence(.i) operation, independent of STB
   end record;
 
   -- bus response --
@@ -171,14 +172,15 @@ package neorv32_package is
 
   -- source (request) termination --
   constant req_terminate_c : bus_req_t := (
-    addr => (others => '0'),
-    data => (others => '0'),
-    ben  => (others => '0'),
-    stb  => '0',
-    rw   => '0',
-    src  => '0',
-    priv => '0',
-    rvso => '0'
+    addr  => (others => '0'),
+    data  => (others => '0'),
+    ben   => (others => '0'),
+    stb   => '0',
+    rw    => '0',
+    src   => '0',
+    priv  => '0',
+    rvso  => '0',
+    fence => '0'
   );
 
   -- endpoint (response) termination --
@@ -527,8 +529,7 @@ package neorv32_package is
     lsu_req      : std_ulogic;                     -- trigger memory access request
     lsu_rw       : std_ulogic;                     -- 0: read access, 1: write access
     lsu_mo_we    : std_ulogic;                     -- memory address and data output register write enable
-    lsu_fence    : std_ulogic;                     -- fence operation
-    lsu_fencei   : std_ulogic;                     -- fence.i operation
+    lsu_fence    : std_ulogic;                     -- fence(.i) operation
     lsu_priv     : std_ulogic;                     -- effective privilege level for load/store
     -- instruction word --
     ir_funct3    : std_ulogic_vector(02 downto 0); -- funct3 bit field
@@ -559,7 +560,6 @@ package neorv32_package is
     lsu_rw       => '0',
     lsu_mo_we    => '0',
     lsu_fence    => '0',
-    lsu_fencei   => '0',
     lsu_priv     => '0',
     ir_funct3    => (others => '0'),
     ir_funct12   => (others => '0'),