[docs] fix broken WISHBONE links

stnolting · Oct 31, 2023 · b74efe5 · b74efe5
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diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
@@ -29,7 +29,7 @@ image::neorv32_processor.png[align=center]
 * _optional_ 8-bit serial data device interface (<<_serial_data_interface_controller_spi,**SDI**>>)
 * _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
 * _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
-* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
+* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone,**WISHBONE**>>)
 * _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
 * _optional_ PWM controller with up to 12 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
 * _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)

diff --git a/docs/userguide/adding_custom_hw_modules.adoc b/docs/userguide/adding_custom_hw_modules.adoc
@@ -32,7 +32,7 @@ software handling ("bit-banging" for the GPIO). Hence, it is not recommend to us
 
 === External Bus Interface
 
-The https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite[External Bus Interface]
+The https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone[External Bus Interface]
 provides the classic approach for attaching custom IP. By default, the bus interface implements the widely adopted
 Wishbone interface standard. This project also includes wrappers to convert to other protocol standards like ARM's
 AXI4-Lite or Intel's Avalon protocols. By using a full-featured bus protocol, complex SoC designs can be implemented
@@ -81,7 +81,7 @@ chip-internal extension options:
 
 * https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu[Custom Functions Unit (CFU)] for CPU-internal custom RISC-V instructions
 * https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs[Custom Functions Subsystem (CFS)] for tightly-coupled processor-internal co-processors
-* https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite[External Bus Interface (WISHBONE)] for processor-external memory-mapped modules
+* https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone[External Bus Interface (WISHBONE)] for processor-external memory-mapped modules
 
 .Comparison of On-Chip Extension Options
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