[cpu] add page fault trigger stubs

rtl/core/neorv32_cpu.vhd

@@ -133,6 +133,9 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
   signal link_pc      : std_ulogic_vector(XLEN-1 downto 0); -- link pc (return address)
   signal pmp_ex_fault : std_ulogic; -- PMP instruction fetch fault
   signal pmp_rw_fault : std_ulogic; -- PMP read/write access fault
+  signal i_page_fault : std_ulogic; -- instruction page fault
+  signal l_page_fault : std_ulogic; -- load page fault
+  signal s_page_fault : std_ulogic; -- store page fault
 
 begin
 
@@ -211,7 +214,7 @@ begin
     rstn_i         => rstn_i,         -- global reset, low-active, async
     ctrl_o         => ctrl,           -- main control bus
     -- instruction fetch interface --
-    i_page_fault_i => '0',            -- instruction fetch page fault
+    i_page_fault_i => i_page_fault,   -- instruction fetch page fault
     i_pmp_fault_i  => pmp_ex_fault,   -- instruction fetch pmp fault
     bus_req_o      => ibus_req_o,     -- request
     bus_rsp_i      => ibus_rsp_i,     -- response
@@ -243,8 +246,8 @@ begin
     ma_store_i     => ma_store,       -- misaligned store data address
     be_load_i      => be_load,        -- bus error on load data access
     be_store_i     => be_store,       -- bus error on store data access
-    l_page_fault_i => '0',            -- load page fault
-    s_page_fault_i => '0'             -- store page fault
+    l_page_fault_i => l_page_fault,   -- load page fault
+    s_page_fault_i => s_page_fault    -- store page fault
   );
 
   -- external CSR read-back --
@@ -391,4 +394,12 @@ begin
   end generate;
 
 
+  -- Memory Management/Paging Unit ----------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  -- nothing to see here yet --
+  i_page_fault <= '0'; -- instruction page fault
+  l_page_fault <= '0'; -- load page fault
+  s_page_fault <= '0'; -- store page fault
+
+
 end neorv32_cpu_rtl;