Merge branch 'main' into linty_test

Signed-off-by: stnolting <[email protected]>
stnolting · Nov 2, 2024 · fea96e0 · fea96e0
2 parents f846ec7 + 3cf72cc
commit fea96e0
Show file tree

Hide file tree

Showing 111 changed files with 3,119 additions and 3,008 deletions.
diff --git a/.github/workflows/Processor.yml b/.github/workflows/Processor.yml
@@ -17,25 +17,9 @@ on:
 
 jobs:
 
-  Software:
+  sim_default_tb:
     runs-on: ubuntu-latest
-    container: ghcr.io/stnolting/neorv32/sim
-
-    steps:
-
-    - name: '🧰 Repository Checkout'
-      uses: actions/checkout@v4
-
-    - name: '⚙️ Build Software Framework Tests'
-      run: |
-        make -C sw/example/processor_check check
-        make -C sw/example clean_all exe
-        make -C sw/bootloader clean_all info bootloader
-
-
-  Simple:
-    runs-on: ubuntu-latest
-    name: 'Simple testbench'
+    name: 'processor simulation'
     strategy:
       fail-fast: false
       matrix:
@@ -48,50 +32,32 @@ jobs:
     - name: '🧰 Repository Checkout'
       uses: actions/checkout@v4
 
-    - name: '🚧 Build and install software; then simulate with shell script'
-      uses: docker://ghcr.io/stnolting/neorv32/sim
-      # Redirect UART0 TX to text.io simulation output via <UARTx_SIM_MODE> user flags
-      with:
-        args: >-
-          make -C sw/example/${{ matrix.example }}
-          clean_all
-          USER_FLAGS+="-DUART0_SIM_MODE -DUART1_SIM_MODE -flto"
-          EFFORT=-Os
-          MARCH=rv32ima_zicsr_zifencei
-          info
-          all
-          sim-check
-
-
-  VUnit:
-    runs-on: ubuntu-latest
-
-    steps:
+    - name: '📦 Install RISC-V GCC'
+      run: |
+        wget -q https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv32i-131023/riscv32-unknown-elf.gcc-13.2.0.tar.gz
+        mkdir $GITHUB_WORKSPACE/riscv-gcc
+        tar -xzf riscv32-unknown-elf.gcc-13.2.0.tar.gz -C $GITHUB_WORKSPACE/riscv-gcc
+        echo $GITHUB_WORKSPACE/riscv-gcc/bin >> $GITHUB_PATH
 
-    - name: '🧰 Repository Checkout'
-      uses: actions/checkout@v4
+    - name: '📦 Install GHDL'
+      uses: ghdl/setup-ghdl-ci@nightly
 
-    - name: '⚙️ Build and install Processor Check software'
-      uses: docker://ghcr.io/stnolting/neorv32/sim
-      with:
-        args: >-
-          make -C sw/example/processor_check
-          clean_all
-          USER_FLAGS+=-DUART0_SIM_MODE
-          USER_FLAGS+=-DSUPPRESS_OPTIONAL_UART_PRINT
-          USER_FLAGS+=-flto
-          MARCH=rv32imac_zicsr_zifencei
-          info
-          all
+    - name: '🔍 Check tools'
+      run: |
+        riscv32-unknown-elf-gcc -v
+        ghdl -v
 
-    - name: '📤 Archive Processor Check application image'
-      uses: actions/upload-artifact@v4
-      with:
-        name: application
-        path: rtl/core/neorv32_application_image.vhd
+    - name: '⚙️ Build Software Framework Tests'
+      run: |
+        make -C sw/example/processor_check check
+        make -C sw/example clean_all exe
+        make -C sw/bootloader clean_all info bootloader
 
-    - name: '🚧 Run Processor Hardware Tests with VUnit'
-      uses: VUnit/vunit_action@master
-      with:
-        image: ghcr.io/stnolting/neorv32/sim
-        cmd: ./sim/run.py --ci-mode -v
+    - name: '🚧 Compile executable and run simulation'
+      run: |
+        make -C sw/example/${{ matrix.example }} \
+        USER_FLAGS+="-DUART0_SIM_MODE -DUART1_SIM_MODE" \
+        clean_all \
+        info \
+        all \
+        sim-check
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,14 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 02.11.2024 | 1.10.6.2 | :warning: rework processor boot configuration; add new boot-configuration generics | [#1086](https://github.com/stnolting/neorv32/pull/1086) |
+| 01.11.2024 | 1.10.6.1 | :test_tube: convert VHDL memory images into full-scale VHDL packages | [#1084](https://github.com/stnolting/neorv32/pull/1084) |
+| 26.10.2024 | [**:rocket:1.10.6**](https://github.com/stnolting/neorv32/releases/tag/v1.10.6) | **New release** | |
+| 26.10.2024 | 1.10.5.11 | cleanup central makefile and linker script | [#1077](https://github.com/stnolting/neorv32/pull/1077) |
+| 21.10.2024 | 1.10.5.10 | :test_tube: rework linker script's ROM/IMEM default size (=16kB); add customization variable to all makefiles in `sw/example` | [#1072](https://github.com/stnolting/neorv32/pull/1072) |
+| 20.10.2024 | 1.10.5.9 | :warning: rework XIRQ controller; remove "interrupt pending" register `EIP` | [#1071](https://github.com/stnolting/neorv32/pull/1071) |
+| 18.10.2024 | 1.10.5.8 | minor RTL code cleanups | [#1068](https://github.com/stnolting/neorv32/pull/1068) |
+| 18.10.2024 | 1.10.5.7 | use individual/new module for XBUS-to-AXI4-Lite bridge | [#1063](https://github.com/stnolting/neorv32/pull/1063) |
 | 12.10.2024 | 1.10.5.6 | :warning: remove legacy support for on-chip debugger DM version v0.13; now only supporting DM v1.0 (removing `OCD_DM_LEGACY_MODE` generic) | [#1056](https://github.com/stnolting/neorv32/pull/1056) |
 | 11.10.2024 | 1.10.5.5 | :sparkles: :lock: add support for optional on-chip debugger authentication; :warning: rename OCD-related top generics | [#1053](https://github.com/stnolting/neorv32/pull/1053) |
 | 06.10.2024 | 1.10.5.4 | :warning: rework PWM module | [#1049](https://github.com/stnolting/neorv32/pull/1049) |
@@ -143,7 +151,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 | 16.02.2024 | 1.9.5.2 | :warning: **revert** support for page faults (keep that in mmu branch for now) | [#809](https://github.com/stnolting/neorv32/pull/809) |
 | 16.02.2024 | 1.9.5.1 | :sparkles: add two new generics to exclude certain PMP modes from synthesis | [#808](https://github.com/stnolting/neorv32/pull/808) |
 | 16.02.2024 | [**:rocket:1.9.5**](https://github.com/stnolting/neorv32/releases/tag/v1.9.5) | **New release** | |
-| 15.02.2023 | 1.9.4.13 | allow the DMA to issue a FENCE operation | [#807](https://github.com/stnolting/neorv32/pull/807) |
+| 15.02.2024 | 1.9.4.13 | allow the DMA to issue a FENCE operation | [#807](https://github.com/stnolting/neorv32/pull/807) |
 | 14.02.2024 | 1.9.4.12 | :lock: close another illegal compressed instruction encoding loophole | [#806](https://github.com/stnolting/neorv32/pull/806) |
 | 11.02.2024 | 1.9.4.11 | :bug: fix several FPU bugs and design flaws | [#794](https://github.com/stnolting/neorv32/pull/794) |
 | 11.02.2024 | 1.9.4.10 | minor additions to previous version (1.9.4.9): fix HPM configuration read-back | [#804](https://github.com/stnolting/neorv32/pull/804) |

diff --git a/README.md b/README.md
@@ -56,26 +56,25 @@ not working as expected. See how to [contribute](https://github.com/stnolting/ne
 
 - [x] all-in-one package: **CPU** + **SoC** + **Software Framework & Tooling**
 - [x] completely described in behavioral, platform-independent VHDL - **no** platform-specific primitives, macros, attributes, etc.; an all-Verilog "version" is also [available](https://github.com/stnolting/neorv32-verilog)
-- [x] extensive configuration options for adapting the processor to the requirements of the application
-- [x] highly [extensible hardware](https://stnolting.github.io/neorv32/ug/#_comparative_summary) - on CPU, processor and system level
+- [x] extensive configuration options for adapting the processor to the requirements of the application (on CPU, processor and system level)
 - [x] aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
 - [x] FPGA friendly (e.g. _all_ internal memories can be mapped to block RAM - including the CPU's register file)
 - [x] optimized for high clock frequencies to ease integration / timing closure
-- [x] from zero to _"hello world!"_ - completely open source and documented
-- [x] highly documented - on software and hardware side
+- [x] from zero to _"hello world!"_ - completely open source and documented (on software and hardware side)
 - [x] easy to use even for FPGA / RISC-V starters – intended to work _out of the box_
 
 ### Project Status
 
 [![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
 [![commits-since-latest-release](https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/activity)
 
-| Task / Subproject                                  | Repository | CI Status |
-|:---------------------------------------------------|:-----------|:----------|
+| Task / Subproject | Repository | CI Status |
+|:------------------|:-----------|:----------|
 | Code quality ([Linty](https://linty-services.com)) | [neorv32](https://github.com/stnolting/neorv32)                       | [![Quality Gate Status](https://oss.linty-services.com/api/project_badges/measure?project=neorv32&metric=alert_status&token=sqb_97b392f36051f7887215e61c53d6f0f858ca2697)](https://oss.linty-services.com/dashboard?id=neorv32) |
 | GitHub pages (docs)                                | [neorv32](https://github.com/stnolting/neorv32)                       | [![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32) |
 | Build documentation                                | [neorv32](https://github.com/stnolting/neorv32)                       | [![Documentation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main&longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation) |
 | Processor verification                             | [neorv32](https://github.com/stnolting/neorv32)                       | [![Processor](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main&longCache=true&style=flat-square&label=Processor%20Check&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor) |
+| VUnit testbench                                    | [neorv32-vunit](https://github.com/stnolting/neorv32-vunit)           | [![neorv32-vunit](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-vunit/vunit.yml?branch=main&longCache=true&style=flat-square&label=neorv32-vunit&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-vunit/actions/workflows/vunit.yml) |
 | RISCOF core verification                           | [neorv32-riscof](https://github.com/stnolting/neorv32-riscof)         | [![neorv32-riscof](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-riscof/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-riscof&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml) |
 | FPGA implementations                               | [neorv32-setups](https://github.com/stnolting/neorv32-setups)         | [![Implementation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Implementation.yml?branch=main&longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation) |
 | All-Verilog version                                | [neorv32-verilog](https://github.com/stnolting/neorv32-verilog)       | [![neorv32-verilog](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-verilog/main.yml?branch=main&longCache=true&style=flat-square&label=neorv32-verilog&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml) |

diff --git a/docs/attrs.adoc b/docs/attrs.adoc
@@ -2,7 +2,7 @@
 :email: [email protected]
 :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic, safety
 :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.10.5
+:revnumber: v1.10.6
 :doctype: book
 :sectnums:
 :stem:

diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc
@@ -531,6 +531,7 @@ The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.
 |=======================
 | Class | Instructions | Execution cycles
 | ALU           | `add[i]` `slt[i]` `slt[i]u` `xor[i]` `or[i]` `and[i]` `sub` `lui` `auipc` | 2
+| No-operation  | "`nop`"                                                                   | 2
 | ALU shifts    | `sll[i]` `srl[i]` `sra[i]`                                                | 3 + 1..32; FAST_SHIFT: 4
 | Branches      | `beq` `bne` `blt` `bge` `bltu` `bgeu`                                     | taken: 6; not taken: 3
 | Jump/call     | `jal[r]`                                                                  | 6

diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc
@@ -360,7 +360,7 @@ As software does not need to determine the interrupt cause the reduction in late
 |=======================
 | Name        | Machine exception program counter
 | Address     | `0x341`
-| Reset value | `0x00000000`
+| Reset value | `BOOT_ADDR` (CPU boot address, see <<_cpu_top_entity_generics>>)
 | ISA         | `Zicsr`
 | Description | The `mepc` CSR provides the instruction address where execution has stopped/failed when
 an interrupt is triggered / an exception is raised. See section <<_traps_exceptions_and_interrupts>> for a list of all legal values.

diff --git a/docs/datasheet/overview.adoc b/docs/datasheet/overview.adoc
@@ -179,7 +179,7 @@ All core VHDL files from the list below have to be assigned to a **new library**
 [NOTE]
 See section <<_file_list_files>> for more information.
 
-.RTL File List and Hierarchy
+.RTL File List and Hierarchy (in alphabetical order)
 ...................................
 neorv32_top.vhd                 - NEORV32 PROCESSOR/SOC TOP ENTITY
 │
@@ -199,7 +199,7 @@ neorv32_top.vhd                 - NEORV32 PROCESSOR/SOC TOP ENTITY
 │└neorv32_cpu_regfile.vhd       - Data register file
 │
 ├neorv32_boot_rom.vhd           - Bootloader ROM
-│└neorv32_bootloader_image.vhd  - Bootloader ROM memory image
+│└neorv32_bootloader_image.vhd  - Bootloader ROM memory image (package)
 ├neorv32_bus.vhd                - SoC bus infrastructure modules
 ├neorv32_cache.vhd              - Generic cache module
 ├neorv32_cfs.vhd                - Custom functions subsystem
@@ -214,7 +214,7 @@ neorv32_top.vhd                 - NEORV32 PROCESSOR/SOC TOP ENTITY
 ├neorv32_gpio.vhd               - General purpose input/output port unit
 ├neorv32_gptmr.vhd              - General purpose 32-bit timer
 ├neorv32_imem.vhd               - Generic processor-internal instruction memory
-│└neorv32_application_image.vhd - IMEM application initialization image
+│└neorv32_application_image.vhd - IMEM application initialization image (package)
 ├neorv32_mtime.vhd              - Machine system timer
 ├neorv32_neoled.vhd             - NeoPixel (TM) compatible smart LED interface
 ├neorv32_onewire.vhd            - One-Wire serial interface controller
@@ -284,7 +284,7 @@ puts $file_list
 
 .File-List Usage Examples
 [TIP]
-The provided file-list files are used by the GHDL-based simple simulation setup (`sim/tb_simple/ghdl.setup.sh`) as
+The provided file-list files are used by the GHDL-based simple simulation setup (`sim/ghdl.setup.sh`) as
 well as by the Vivado IP packager script (`rtl/system_integration/neorv32_vivado_ip.tcl`).