🧪 [linty] initial setup (preliminary)

.github/workflows/Linty.yml

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+name: Linty
+on:
+  pull_request:
+  push:
+
+jobs:
+  linty:
+    name: Linty
+    timeout-minutes: 10
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Git Checkout
+        uses: actions/checkout@v3
+        with:
+          fetch-depth: 0
+
+      - name: Cache
+        uses: actions/[email protected]
+        with:
+          path: ~/.sonar/cache
+          key: sonar
+          restore-keys: sonar
+
+      - name: Run Linty
+        run: |
+          docker run \
+            --rm \
+            -e SONAR_HOST_URL=https://oss.linty-services.com \
+            -e SONAR_TOKEN="${{ secrets.LINTY_TOKEN }}" \
+            -e GITHUB_TOKEN="${{ secrets.GITHUB_TOKEN }}" \
+            -e GITHUB_REPOSITORY_OWNER="$GITHUB_REPOSITORY_OWNER" \
+            -e GITHUB_REPOSITORY="$GITHUB_REPOSITORY" \
+            -e TABBY_CAD_LICENSE="$TABBY_CAD_LICENSE" \
+            -v "$PWD:/usr/src" \
+            lintyservices/linty-scanner:latest
+        env:
+          TABBY_CAD_LICENSE: ${{ secrets.TABBY_CAD_LICENSE }}
+
+      - name: Debug
+        if: always()
+        uses: actions/upload-artifact@v3
+        with:
+          name: debug
+          path: |
+            .linty/

hierarchy.ys

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+hierarchy -top neorv32_ProcessorTop_UP5KDemo

read.ys

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+verific -work neorv32 -vhdl ./rtl/core/neorv32_package.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_sys.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_clockgate.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_fifo.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_decompressor.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_control.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_regfile.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_cp_shifter.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_cp_muldiv.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_cp_bitmanip.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_cp_fpu.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_cp_cfu.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_cp_cond.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_alu.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_lsu.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu_pmp.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cpu.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_bus.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cache.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_dma.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_imem.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_dmem.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_boot_rom.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_xip.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_xbus.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_cfs.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_sdi.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_gpio.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_wdt.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_mtime.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_uart.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_spi.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_twi.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_pwm.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_trng.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_neoled.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_xirq.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_gptmr.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_onewire.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_slink.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_crc.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_sysinfo.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_debug_dtm.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_debug_dm.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_top.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_application_image.vhd
+verific -work neorv32 -vhdl ./rtl/core/neorv32_bootloader_image.vhd
+
+verific -L neorv32 -vhdl ./rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd

sona-project.properties

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+sonar.projectKey=neorv32
+sonar.sources=./rtl,./sim
+sonar.hdl.file.simulationPaths=./sim/**/*.vhd*
+sonar.hdl.topModule=neorv32_ProcessorTop_UP5KDemo