stnolting · stnolting · Oct 16, 2023 · Oct 14, 2023 · Oct 16, 2023 · Oct 16, 2023
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -5,7 +5,7 @@ Releases are linked and highlighted. The latest release is
 [![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases).
 A list of all releases can be found [here](https://github.com/stnolting/neorv32/releases).
 
-Starting with version `1.5.7` this project uses [semantic versioning](https://semver.org).
+This project uses [semantic versioning](https://semver.org).
 The **version identifier** uses an additional custom element (`MAJOR.MINOR.PATCH.custom`)
 to track individual changes. The identifier is incremented by every core RTL modification
 and also by major software/project changes.
@@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 16.10.2023 | 1.9.0.2 | minor CPU control cleanups and optimizations (branch system); [#707](https://github.com/stnolting/neorv32/pull/707) |
 | 13.10.2023 | 1.9.0.1 | update software framework to GCC-13.2.0; [#705](https://github.com/stnolting/neorv32/pull/705) |
 | 13.10.2023 | [**:rocket:1.9.0**](https://github.com/stnolting/neorv32/releases/tag/v1.9.0) | **New release** |
 | 13.10.2023 | 1.8.9.9 | minor hardware edits and optimizations; [#703](https://github.com/stnolting/neorv32/pull/703) |

diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd
@@ -274,7 +274,7 @@ begin
   -- -------------------------------------------------------------------------------------------
   neorv32_cpu_regfile_inst: entity neorv32.neorv32_cpu_regfile
   generic map (
-    RVE    => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
+    RVE_EN => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
     RS3_EN => regfile_rs3_en_c,      -- enable 3rd read port
     RS4_EN => regfile_rs4_en_c       -- enable 4th read port
   )

diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
diff --git a/rtl/core/neorv32_cpu_regfile.vhd b/rtl/core/neorv32_cpu_regfile.vhd
@@ -53,7 +53,7 @@ use neorv32.neorv32_package.all;
 
 entity neorv32_cpu_regfile is
   generic (
-    RVE    : boolean; -- implement embedded RF extension?
+    RVE_EN : boolean; -- implement embedded RF extension?
     RS3_EN : boolean; -- enable 3rd read port
     RS4_EN : boolean  -- enable 4th read port
   );
@@ -77,7 +77,7 @@ end neorv32_cpu_regfile;
 architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
 
   -- auto-configuration --
-  constant addr_bits_c : natural := cond_sel_natural_f(RVE, 4, 5); -- address width
+  constant addr_bits_c : natural := cond_sel_natural_f(RVE_EN, 4, 5); -- address width
 
   -- register file --
   type   reg_file_t is array ((2**addr_bits_c)-1 downto 0) of std_ulogic_vector(XLEN-1 downto 0);

diff --git a/rtl/core/neorv32_debug_dm.vhd b/rtl/core/neorv32_debug_dm.vhd
@@ -204,8 +204,8 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is
     15 => x"00000073"
   );
 
-  -- access helpers --
-  signal rden, wren : std_ulogic;
+  -- CPU access helpers --
+  signal accen, rden, wren : std_ulogic;
 
   -- Debug Core Interface --
   type dci_t is record
@@ -661,8 +661,9 @@ begin
 
   -- Access Control ------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  rden <= cpu_debug_i and bus_req_i.stb and (not bus_req_i.rw); -- allow access only when in debug mode
-  wren <= cpu_debug_i and bus_req_i.stb and (    bus_req_i.rw); -- allow access only when in debug mode
+  accen <= cpu_debug_i and bus_req_i.stb; -- allow access only when in debug-mode
+  rden  <= accen and (not bus_req_i.rw);
+  wren  <= accen and (    bus_req_i.rw);
 
 
   -- Write Access ---------------------------------------------------------------------------
@@ -687,9 +688,8 @@ begin
       dci.resume_ack    <= '0';
       dci.execute_ack   <= '0';
       dci.exception_ack <= '0';
-      -- NOTE: only check the individual BYTE ACCESSES - not the actual write data --
       if (bus_req_i.addr(7 downto 6) = dm_sreg_base_c(7 downto 6)) and (wren = '1') then
-        dci.halt_ack      <= bus_req_i.ben(sreg_halt_ack_c/8);
+        dci.halt_ack      <= bus_req_i.ben(sreg_halt_ack_c/8); -- [NOTE] use the individual BYTE ENABLES and not the actual write data
         dci.resume_ack    <= bus_req_i.ben(sreg_resume_ack_c/8);
         dci.execute_ack   <= bus_req_i.ben(sreg_execute_ack_c/8);
         dci.exception_ack <= bus_req_i.ben(sreg_exception_ack_c/8);
@@ -703,7 +703,7 @@ begin
   read_access: process(clk_i)
   begin
     if rising_edge(clk_i) then
-      bus_rsp_o.ack  <= rden or wren;
+      bus_rsp_o.ack  <= accen;
       bus_rsp_o.data <= (others => '0');
       if (rden = '1') then -- output enable
         case bus_req_i.addr(7 downto 6) is -- module select

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -59,7 +59,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090001"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090002"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width, do not change!
 
@@ -91,7 +91,7 @@ package neorv32_package is
   constant mem_io_base_c   : std_ulogic_vector(31 downto 0) := x"ffffe000";
   constant mem_io_size_c   : natural := 8*1024;
 
-  -- Start of uncached memory access (page / 4MSBs only) --
+  -- Start of uncached memory access (256MB page / 4MSBs only) --
   constant uncached_begin_c  : std_ulogic_vector(31 downto 0) := x"f0000000";
 
   -- IO Address Map --

diff --git a/rtl/core/neorv32_wdt.vhd b/rtl/core/neorv32_wdt.vhd
@@ -224,7 +224,7 @@ begin
         end if;
         -- hardware reset --
         if ((timeout_rst = '1') and (prsc_tick = '1')) or -- timeout
-           ((ctrl.strict = '1') and (reset_force = '1')) then -- strict mode and incorrect password / locked CTRL write attempt
+           ((ctrl.strict = '1') and (reset_force = '1')) then -- strict mode and incorrect password
           hw_rst <= '1';
         end if;
       end if;

diff --git a/sw/example/processor_check/main.c b/sw/example/processor_check/main.c
@@ -1710,6 +1710,7 @@ int main() {
   register uint32_t syscall_a0 asm ("a0");
   register uint32_t syscall_a1 asm ("a1");
   register uint32_t syscall_a2 asm ("a2");
+  uint32_t syscall_res = 0;
 
   // try to execute service call in user mode
   // hart will be back in MACHINE mode when trap handler returns
@@ -1719,7 +1720,8 @@ int main() {
     syscall_a1 = 12000;
     syscall_a2 = 628;
 
-    asm ("ecall" : "=r" (syscall_a0) : "r" (syscall_a0), "r" (syscall_a1), "r" (syscall_a2));
+    asm volatile ("ecall" : "=r" (syscall_a0) : "r" (syscall_a0), "r" (syscall_a1), "r" (syscall_a2));
+    syscall_res = syscall_a0; // backup result before a0 is used for something else
   }
 
   // restore initial trap handlers
@@ -1728,7 +1730,7 @@ int main() {
 
   if (((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MENV_CALL) ||
        (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_UENV_CALL)) &&
-       (syscall_a0 == 12628)) { // correct "service" result
+       (syscall_res == 12628)) { // correct "service" result
     test_ok();
   }
   else {