7. Get the core to synthesize

TEMP / TODO

• Replace Quartus/Intel specific elements like RAMs/ROMs
• Fix errors (see below)
• Be prepared that there are subtle differences between Quartus/Intel and Vivado/Xilinx (share C1541 story)

Here are some explanations from MJoergen collected during the port of the C64:

3. Fixing errors during elaboration

At this stage, the core is now properly added to the project. However, the work is still far from over. It seems the Vivado tool for Xilinx FPGA's is less forgiving than the Quartus tool for Intel FPGA's. So a number of minor edits are needed in the source files of the core in order for Vivado to work with them. This is where it is convenient to have made a separate branch of a private fork of the MiSTer core.

To get a report of the errors to be fixed click the Open Elaboration option. This will show the error. Unfortunately, only one error is shown each time. So the process is to fix this single error, and then to repeat the process until no more elaboration errors are shown.

3.1. [Synth 8-2576] procedural assignment to a non-register <name> is not permitted

This error is caused by not declaring a register using the reg keyword. Even a purely combinatorial signal will be treated as a register, if it is assigned to within an always_comb block. The fix is to add the reg keyword to the declaration of the register mentioned in the error.

3.2. [Synth 8-1873] declarations not allowed in unnamed block

This error occurs when declaring local signal within an always block. Apparently this is not allowed. However, the fix is very easy. Just add a label after the begin keyword.

3.3. [Synth 8-2671] single value range is not allowed in this mode of verilog

This error is because Vivado tries to auto-detect whether a source file a pure verilog or SystemVerilog based on the file extension (.v versus .sv). In this case a file was erroneously classified a pure verilog. The fix is to locate the file in the Sources tab and then in the Source File Properties tab to change the Type from Verilog to SystemVerilog.

@TODO @TODO @TODO @TODO @TODO

"port map is not a static name or globally static expression" => switch to VHDL 2008

[Synth 8-9339] data object 'old_vs' is already declared ["/media/psf/Home/Desktop/GalagaMEGA65/CORE/Arcade-Galaga_MiSTer/sys/arcade_video.v":264] => Bad practice: old_vs is being used in two separate always @(posedge CLK_VIDEO) blocks. This can lead to issues and is not the best practice in Verilog. To handle this situation, you can create two separate variables for each