DRAM: fast_get() cache-handling improvements
#9817
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When multiple users access the same DRAM data via the fast_get() API, they can run on different cores. The data is immutable, but when initially pointing to it, cache has to be invalidated. Signed-off-by: Guennadi Liakhovetski <[email protected]>
fast_get entry list is global, it can be accessed from any core, allocate it uncached. Signed-off-by: Guennadi Liakhovetski <[email protected]>
Invert a condition to eliminate a single goto. Signed-off-by: Guennadi Liakhovetski <[email protected]>
lyakh
requested review from
kv2019i,
iuliana-prodan,
dbaluta and
abonislawski
as code owners
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SOFCI TEST |
kv2019i
approved these changes
Feb 10, 2025
lgirdwood
approved these changes
Feb 10, 2025
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CI: 1 alsabat failure on HDA MTL https://sof-ci.01.org/sofpr/PR9817/build10578/devicetest/index.html?model=MTLP_RVP_HDA&testcase=check-alsabat-headset-capture-997, TGL nocodec not tested, but the LNL failure puzzles me... https://sof-ci.01.org/sofpr/PR9817/build10577/devicetest/index.html but it absolutely cannot be caused by this PR. This PR changes behaviour of |
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SOFCI TEST |
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CI: now ACE (MTL), cAVE and LNL are all green (except for a single untested system in each), and PTL is just not fully configured yet in CI |
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Use uncached aliases for potentially shared objects, synchronise cache properly when sharing cached access