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topology: enable pcm rate setting from top level m4 #92

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topology: enable pcm rate setting from top level m4 #92

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12 changes: 12 additions & 0 deletions topology/m4/pipeline.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,8 @@ define(`PIPELINE_PCM_ADD',
`undefine(`SCHEDULE_DEADLINE')'
`undefine(`SCHEDULE_PRIORITY')'
`undefine(`SCHEDULE_CORE')'
`undefine(`PCM_MIN_RATE')'
`undefine(`PCM_MAX_RATE')'
`define(`PIPELINE_ID', $2)'
`define(`PCM_ID', $3)'
`define(`PIPELINE_CHANNELS', $4)'
Expand All @@ -51,6 +53,8 @@ define(`PIPELINE_PCM_ADD',
`define(`SCHEDULE_DEADLINE', $7)'
`define(`SCHEDULE_PRIORITY', $8)'
`define(`SCHEDULE_CORE', $9)'
`define(`PCM_MIN_RATE', $10)'
`define(`PCM_MAX_RATE', $11)'
`include($1)'
`DEBUG_PCM_ADD($1, $3)'
)
Expand All @@ -72,6 +76,8 @@ define(`PIPELINE_PCM_DAI_ADD',
`undefine(`DAI_INDEX')'
`undefine(`DAI_FORMAT')'
`undefine(`DAI_PERIODS')'
`undefine(`PCM_MIN_RATE')'
`undefine(`PCM_MAX_RATE')'
`define(`PIPELINE_ID', $2)'
`define(`PCM_ID', $3)'
`define(`PIPELINE_CHANNELS', $4)'
Expand All @@ -85,6 +91,8 @@ define(`PIPELINE_PCM_DAI_ADD',
`define(`DAI_FORMAT', $12)'
`define(`DAI_PERIODS', $13)'
`define(`DAI_NAME', $10$11)'
`define(`PCM_MIN_RATE', $14)'
`define(`PCM_MAX_RATE', $15)'
`include($1)'
)

Expand All @@ -99,13 +107,17 @@ define(`PIPELINE_ADD',
`undefine(`SCHEDULE_DEADLINE')'
`undefine(`SCHEDULE_PRIORITY')'
`undefine(`SCHEDULE_CORE')'
`undefine(`PCM_MIN_RATE')'
`undefine(`PCM_MAX_RATE')'
`define(`PIPELINE_ID', $2)'
`define(`PIPELINE_CHANNELS', $3)'
`define(`PIPELINE_FORMAT', $4)'
`define(`SCHEDULE_FRAMES', $5)'
`define(`SCHEDULE_DEADLINE', $6)'
`define(`SCHEDULE_PRIORITY', $7)'
`define(`SCHEDULE_CORE', $8)'
`define(`PCM_MIN_RATE', $9)'
`define(`PCM_MAX_RATE', $10)'
`include($1)'
)

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8 changes: 4 additions & 4 deletions topology/sof-apl-da7219.m4
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Expand Up @@ -32,26 +32,26 @@ DEBUG_START
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)
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@juimonen can we remove the 48 here, since it can be derived now from the min/max rates. This may need an ABI update and a pipeline update since we will be sending min/max rate with topology and runtime rate via hw_params.

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@lgirdwood sorry I didn't get it...? isn't the 48 like frames per scheduling slice (1000 us in this case). Min and max rates define the range of sample rates that the pipeline accepts. So, I mean aren't these values orthogonal? For e.g. I could have range 8000-192000Hz and scheduling of, say, 108 frames per 1020 us?

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@juimonen I think the logic is that we have a constant sample rate and a schedule time, meaning our processing size is always rate / schedule time.
Variable sample rate components would know their schedule time and would have to determine how many samples to produce/consume every time they are scheduled. Does this make sense ?

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@lgirdwood ok I see. The difficulty is that if we have only min and max rate, it might be that neither of them is the "main" constant sample rate. For e.g. if range is 8-192kHz, the SSP/ADC might be running 44.1/48 kHz and SRC converts other rates. Also on speech capture pipeline we might be running 16kHz main rate but SRC can do from 8-192kHz.

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@juimonen the intention is that the real run time rate will be passed in during hw_params(), this is then propagated through the pipeline from host component to DAI. The components will then have a chance to calculate samples per schedule based on the real rate. If an SRC is in the pipeline then it can alter the rate downstream or upstream of it so the subsequent components will use the SRC rate.


# Low Latency playback pipeline 2 on PCM 1 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
2, 1, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 3 on PCM 1 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
3, 1, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 4 on PCM 0 using max 4 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
#PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4,
4, 99, 4, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 8000, 192000)

#
# DAIs configuration
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6 changes: 5 additions & 1 deletion topology/sof-apl-eq-pcm512x.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,13 @@ include(`platform/intel/bxt.m4')
# PCM0 ----> volume -----> SSP5 (pcm512x)
#

DEBUG_START

# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-eq-volume-playback.m4,
1, 0, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

#
# DAIs configuration
Expand All @@ -53,3 +55,5 @@ DAI_CONFIG(SSP, 5, 0, SSP5-Codec,
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 32, 3, 3),
SSP_CONFIG_DATA(SSP, 5, 24)))

DEBUG_END
6 changes: 3 additions & 3 deletions topology/sof-apl-hdmi.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -33,19 +33,19 @@ dnl frames, deadline, priority, core)
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 2 on PCM 1 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
2, 1, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 3 on PCM 2 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
3, 2, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

#
# DAIs configuration
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26 changes: 13 additions & 13 deletions topology/sof-apl-nocodec.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -44,79 +44,79 @@ dnl frames, deadline, priority, core)
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
2, 0, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 3 on PCM 1 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
3, 1, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 4 on PCM 1 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
4, 1, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 5 on PCM 2 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
5, 2, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 6 on PCM 2 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
6, 2, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 7 on PCM 3 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
7, 3, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 8 on PCM 3 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
8, 3, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 9 on PCM 4 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
9, 4, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 10 on PCM 4 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
10, 4, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 11 on PCM 5 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
11, 5, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 12 on PCM 5 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
12, 5, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Passthrough capture pipeline 13 on PCM 6 using max 4 channels.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4,
13, 6, 4, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 8000, 192000)

#
# DAIs configuration
Expand Down
2 changes: 1 addition & 1 deletion topology/sof-apl-pcm512x.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ DEBUG_START
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

#
# DAIs configuration
Expand Down
8 changes: 4 additions & 4 deletions topology/sof-apl-rt298.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -31,25 +31,25 @@ include(`platform/intel/bxt.m4')
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 5 on PCM 5 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
5, 5, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 6 on PCM 6 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
6, 6, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency playback pipeline 7 on PCM 7 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
7, 7, 2, s16le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)
#
# DAIs configuration
#
Expand Down
20 changes: 10 additions & 10 deletions topology/sof-apl-tdf8532.m4
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Expand Up @@ -36,61 +36,61 @@ include(`platform/intel/bxt.m4')
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-playback.m4,
1, 0, 4, s32le,
48, 1000, 0, 0, SSP, 4, s32le, 2)
48, 1000, 0, 0, SSP, 4, s32le, 2, 48000, 48000)

# Low Latency playback pipeline 2 on PCM 1 using max 8 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-playback.m4,
2, 1, 8, s32le,
48, 1000, 0, 0, SSP, 2, s32le, 2)
48, 1000, 0, 0, SSP, 2, s32le, 2, 48000, 48000)

# Low Latency capture pipeline 3 on PCM 1 using max 8 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4,
3, 1, 8, s32le,
48, 1000, 0, 0, SSP, 2, s32le, 2)
48, 1000, 0, 0, SSP, 2, s32le, 2, 48000, 48000)

# Low Latency playback pipeline 4 on PCM 2 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-playback.m4,
4, 2, 2, s16le,
48, 1000, 0, 0, SSP, 0, s16le, 2)
48, 1000, 0, 0, SSP, 0, s16le, 2, 48000, 48000)

# Low Latency capture pipeline 5 on PCM 2 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4,
5, 2, 2, s16le,
48, 1000, 0, 0, SSP, 0, s16le, 2)
48, 1000, 0, 0, SSP, 0, s16le, 2, 48000, 48000)

# Low Latency capture pipeline 6 on PCM 3 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4,
6, 3, 2, s16le,
48, 1000, 0, 0, SSP, 1, s16le, 2)
48, 1000, 0, 0, SSP, 1, s16le, 2, 48000, 48000)

# Low Latency playback pipeline 7 on PCM 4 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-playback.m4,
7, 4, 2, s16le,
48, 1000, 0, 0, SSP, 3, s16le, 2)
48, 1000, 0, 0, SSP, 3, s16le, 2, 48000, 48000)

# Low Latency capture pipeline 8 on PCM 4 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4,
8, 4, 2, s16le,
48, 1000, 0, 0, SSP, 3, s16le, 2)
48, 1000, 0, 0, SSP, 3, s16le, 2, 48000, 48000)

# Low Latency playback pipeline 9 on PCM 5 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-playback.m4,
9, 5, 2, s16le,
48, 1000, 0, 0, SSP, 5, s16le, 2)
48, 1000, 0, 0, SSP, 5, s16le, 2, 48000, 48000)

# Low Latency capture pipeline 10 on PCM 5 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4,
10, 5, 2, s16le,
48, 1000, 0, 0, SSP, 5, s16le, 2)
48, 1000, 0, 0, SSP, 5, s16le, 2, 48000, 48000)


#
Expand Down
2 changes: 1 addition & 1 deletion topology/sof-apl-wm8804.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ include(`platform/intel/bxt.m4')
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

#
# DAIs configuration
Expand Down
8 changes: 4 additions & 4 deletions topology/sof-bdw-rt286.m4
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Original file line number Diff line number Diff line change
Expand Up @@ -33,25 +33,25 @@ include(`platform/intel/bdw.m4')
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-low-latency-playback.m4,
1, 0, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
2, 0, 2, s32le,
48, 1000, 0, 0)
48, 1000, 0, 0, 48000, 48000)

# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le.
# Schedule 96 frames per 2000us deadline on core 0 with priority 1
PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4,
3, 1, 2, s32le,
96, 2000, 1, 0)
96, 2000, 1, 0, 8000, 192000)

# Tone Playback pipeline 5 using max 2 channels of s32le.
# Schedule 192 frames per 4000us deadline on core 0 with priority 2
PIPELINE_ADD(sof/pipe-tone.m4,
5, 2, s32le,
192, 4000, 2, 0)
192, 4000, 2, 0, 48000, 48000)

# Connect pipelines together
SectionGraph."pipe-bdw-rt286" {
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