Move default_clock declarations to architecture declaration section, …

…for #6

src/psl_abort.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_abort is
 
   signal a, b, c, d : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
   -- Creating an abort signal which is asynchronously set & reset
@@ -26,9 +29,6 @@ begin
   SEQ_C : sequencer generic map ("-_________") port map (clk, c);
   --  D :                         _|________
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion doesn't hold at cycle 4
   WITHOUT_ABORT_a : assert (always a -> next (b before a));
 

src/psl_always.vhd

@@ -15,16 +15,16 @@ architecture psl of psl_always is
 
   signal a : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
   --                            012345
   SEQ : sequencer generic map ("--____") port map (clk, a);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- Beware: potential pitfall!
   -- Every time a PSL assertion is similar to a concurrent
   -- VHDL assertion at that place, it is interpreted as such

src/psl_before.vhd

@@ -17,6 +17,9 @@ architecture psl of psl_before is
   signal c, d : std_logic;
   signal e, f : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -33,9 +36,6 @@ begin
   SEQ_F : sequencer generic map ("_-_______-_") port map (clk, f);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   BEFORE_0_a : assert always (a -> next (b before a))
     report "BEFORE_0_a failed";

src/psl_cover.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_cover is
 
   signal req, busy, done : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -24,9 +27,6 @@ begin
   SEQ_DONE : sequencer generic map ("________-_") port map (clk, done);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- Covers a transfer request
   -- This cover directive holds at cycle 1
   COVER_0_c : cover {req}

src/psl_endpoint.vhd

@@ -16,6 +16,9 @@ architecture psl of psl_endpoint is
   signal a, b : std_logic;
   signal c, d : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -26,9 +29,6 @@ begin
   SEQ_D : sequencer generic map ("____________-_") port map (clk, d);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- only endpoint in psl comment works
   -- psl endpoint ENDPOINT_1_e is {a; b[*3]; c};
 

src/psl_eventually.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_eventually is
 
   signal a, b : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -23,9 +26,6 @@ begin
   SEQ_B : sequencer generic map ("_______-______-_") port map (clk, b);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   -- This assertion leads to a GHDL synthesis crash with bug report
   EVENTUALLY_a : assert always (a -> eventually! b);

src/psl_fell.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_fell is
 
   signal a, b, c : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -24,9 +27,6 @@ begin
   SEQ_C : sequencer generic map ("__-__-___-_") port map (clk, c);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   FELL_0_a : assert always (fell(a) -> c);
 

src/psl_logical_iff.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_logical_iff is
 
   signal a, b, c : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -24,9 +27,6 @@ begin
   SEQ_C : sequencer generic map ("_-__-______") port map (clk, c);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   IFF_0_a : assert always (a <-> b or c);
 

src/psl_logical_implication.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_logical_implication is
 
   signal a, b, c, d : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -25,9 +28,6 @@ begin
   SEQ_D : sequencer generic map ("___________") port map (clk, d);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   IMPLICATION_0_a : assert always (a -> b or c);
 

src/psl_never.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_never is
 
   signal a, b : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -23,9 +26,6 @@ begin
   SEQ_B : sequencer generic map ("__-_") port map (clk, b);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   NEVER_0_a : assert never a;
 

src/psl_next.vhd

@@ -16,6 +16,9 @@ architecture psl of psl_next is
   signal a, b : std_logic;
   signal c, d : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -28,9 +31,6 @@ begin
   SEQ_D : sequencer generic map ("_--__-___--") port map (clk, d);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   NEXT_0_a : assert always (a -> next b);
 

src/psl_next_3.vhd

@@ -17,6 +17,9 @@ architecture psl of psl_next_3 is
   signal c, d : std_logic;
   signal e, f : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -33,9 +36,6 @@ begin
   SEQ_F : sequencer generic map ("_____-----_") port map (clk, f);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   NEXT_0_a : assert always (a -> next[3] (b));
 

src/psl_next_a.vhd

@@ -20,6 +20,9 @@ architecture psl of psl_next_a is
   signal i, j : std_logic;
   signal k, l : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -48,9 +51,6 @@ begin
   SEQ_L : sequencer generic map ("_______-__") port map (clk, l);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion doesn't hold at cycle 6
   NEXT_0_a : assert always (a -> next_a[3 to 5] (b));
 

src/psl_next_e.vhd

@@ -20,6 +20,9 @@ architecture psl of psl_next_e is
   signal i, j : std_logic;
   signal k, l : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -48,9 +51,6 @@ begin
   SEQ_L : sequencer generic map ("_______-__") port map (clk, l);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   NEXT_0_a : assert always (a -> next_e[3 to 5] (b));
 

src/psl_next_event.vhd

@@ -16,6 +16,9 @@ architecture psl of psl_next_event is
   signal a, b, c : std_logic;
   signal d, e, f : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
   --                              012345678901234
@@ -29,9 +32,6 @@ begin
   SEQ_F : sequencer generic map ("____-___-__-___") port map (clk, f);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   NEXT_EVENT_0_a : assert always (a -> next_event(b)(c));
 

src/psl_next_event_4.vhd

@@ -16,6 +16,9 @@ architecture psl of psl_next_event_4 is
   signal a, b, c : std_logic;
   signal d, e, f : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
   --                              0123456789012345
@@ -24,9 +27,6 @@ begin
   SEQ_C : sequencer generic map ("_____-_________-") port map (clk, c);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   NEXT_EVENT_0_a : assert always (a -> next_event(b)[4](c));
 

src/psl_next_event_a.vhd

@@ -18,6 +18,9 @@ architecture psl of psl_next_event_a is
   signal a, c : std_logic;
   signal b    : std_logic_vector(3 downto 0);
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -27,10 +30,6 @@ begin
   SEQ_C : sequencer generic map     ("_____-___---______--_--_") port map (clk, c);
 
 
-
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- Check for one possible value of b
   -- Both assertions hold (see ghdl/ghdl#2157)
   NEXT_EVENT_0_a : assert always ((a and b = x"4") -> next_event_a(c)[1 to 4](b = x"4"))

src/psl_next_event_e.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_next_event_e is
 
   signal a, b, c : std_logic;
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -24,9 +27,6 @@ begin
   SEQ_C : sequencer generic map ("______-___-____") port map (clk, c);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   NEXT_EVENT_0_a : assert always (a -> next_event_e(b)[1 to 2](c));
 

src/psl_onehot.vhd

@@ -15,6 +15,9 @@ architecture psl of psl_onehot is
 
   signal a, b : std_logic_vector(3 downto 0);
 
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
 begin
 
 
@@ -23,9 +26,6 @@ begin
   SEQ_B : hex_sequencer generic map ("111222444888999") port map (clk, b);
 
 
-  -- All is sensitive to rising edge of clk
-  default clock is rising_edge(clk);
-
   -- This assertion holds
   ONEHOT_0_a : assert always onehot(a);