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9 public repositories
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RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
Updated
Dec 22, 2022
Verilog
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
Updated
Jan 16, 2023
Verilog
DLX architecture simulator written in TypeScript & React
Updated
Jan 27, 2024
TypeScript
Digital design and synthesis of a DLX processor in VHDL
Updated
Mar 17, 2019
VHDL
Emulator for the DLX-Processor
Optimization of matrix computation in a low-level language
Updated
May 14, 2019
Assembly
SDLX - Simplified DLX processor in Verilog
Updated
Apr 8, 2023
Verilog
Implementacion de la práctica desarrollada de WinDLX a lo largo del curso 23-24 de Arquitectura de Computadores (USAL)
Updated
Oct 31, 2024
Assembly
Computer Architectures - Practical Assignment #2:
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