🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Updated
Dec 3, 2024 - VHDL
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.
Delivrables and code base from a CentraleSupéléc project
Simulating the NEORV32 RISC-V Processor using the VUnit testing framework.
A LeNet-5 implementation using C language and FPGA, obtaining more performance (Hardware) together with greater versatility (Software), uniting the two worlds. Hardening the Software and Softening the Hardware, to something in between, like Molten Iron, so a Moltenware implementation.
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