SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

CMake for Xilinx Vivado/Vitis

HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Canny edge detection in HLS

Comprehensive open-source curriculum for mastering heterogeneous computing architectures and optimization.

Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

Xilinx Tools Tutorials

Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.

A TFTP server running on Zynq-7000

FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.

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