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spiOverJtag: Xilinx spartan7 xc7s6ftgb196 bitstream
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trabucayre committed Aug 1, 2024
1 parent a509a28 commit 406a6ba
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Showing 4 changed files with 12 additions and 1 deletion.
2 changes: 1 addition & 1 deletion spiOverJtag/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ XILINX_PARTS := xc3s500evq100 \
xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \
xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
xc7a200tsbg484 xc7a200tfbg484 xc7a200tfbg676\
xc7s25csga225 xc7s25csga324 xc7s50csga324 \
xc7s6ftgb196 xc7s25csga225 xc7s25csga324 xc7s50csga324 \
xc7k70tfbg484 xc7k70tfbg676 \
xc7k160tffg676 \
xc7k325tffg676 xc7k325tffg900 \
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1 change: 1 addition & 0 deletions spiOverJtag/build.py
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Expand Up @@ -106,6 +106,7 @@
"xc7k325tffg900" : "xc7k_ffg900",
"xc7k420tffg901" : "xc7k_ffg901",
"xc7vx330tffg1157" : "xc7v_ffg1157",
"xc7s6ftgb196" : "xc7s_ftgb196",
"xc7s25csga225" : "xc7s_csga225",
"xc7s25csga324" : "xc7s_csga324",
"xc7s50csga324" : "xc7s_csga324",
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10 changes: 10 additions & 0 deletions spiOverJtag/constr_xc7s_ftgb196.xdc
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@@ -0,0 +1,10 @@
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
Binary file added spiOverJtag/spiOverJtag_xc7s6ftgb196.bit.gz
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