[VXX][test] reorganize test target names

triSYCL · Jul 5, 2022 · a326f83 · a326f83
1 parent 018a553
commit a326f83
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Showing 2 changed files with 12 additions and 12 deletions.
diff --git a/sycl/doc/GettingStartedXilinxFPGA.md b/sycl/doc/GettingStartedXilinxFPGA.md
@@ -1105,9 +1105,9 @@ Note that the SPIR compilation flow has been discontinued.
 ```bash
   cd $SYCL_HOME/llvm/build
   # Running tests with the OpenCL backend
-  cmake --build . --parallel `nproc` --target check-sycl-vitis
+  cmake --build . --parallel `nproc` --target check-sycl-vitis-opencl
   # Running tests with the XRT backend
-  cmake --build . --parallel `nproc` --target check-sycl-xrt
+  cmake --build . --parallel `nproc` --target check-sycl-vitis-xrt
 ```
 
 This takes usually 45-60 minutes with a good CPU.
@@ -1117,9 +1117,9 @@ This takes usually 45-60 minutes with a good CPU.
 ```bash
   cd $SYCL_HOME/llvm/build
   # Running tests with the OpenCL backend
-  cmake --build . --parallel `nproc` --target check-sycl-vitis-hw
+  cmake --build . --parallel `nproc` --target check-sycl-vitis-opencl-hw
   # Running tests with the XRT backend
-  cmake --build . --parallel `nproc` --target check-sycl-xrt-hw
+  cmake --build . --parallel `nproc` --target check-sycl-vitis-xrt-hw
 ```
 
 This takes usually 10+ hours.

diff --git a/sycl/test/CMakeLists.txt b/sycl/test/CMakeLists.txt
@@ -69,41 +69,41 @@ add_lit_testsuite(check-sycl-vitis-cpu "Running the SYCL vitis regression test o
   )
 set_target_properties(check-sycl-vitis-cpu PROPERTIES FOLDER "SYCL tests")
 
-add_lit_testsuite(check-sycl-vitis "Running the SYCL regression tests for sycl-vitis hw_emu"
+add_lit_testsuite(check-sycl-vitis-opencl "Running the SYCL regression tests for sycl-vitis hw_emu"
   ${CMAKE_CURRENT_BINARY_DIR}/vitis
   ARGS ${RT_TEST_ARGS}
   PARAMS "VITIS=only;SYCL_TRIPLE=fpga64_hls_hw_emu-xilinx-linux;SYCL_PLUGIN=opencl"
   DEPENDS ${SYCL_TEST_DEPS}
   EXCLUDE_FROM_CHECK_ALL
   )
-set_target_properties(check-sycl-vitis PROPERTIES FOLDER "SYCL tests")
+set_target_properties(check-sycl-vitis-opencl PROPERTIES FOLDER "SYCL tests")
 
-add_lit_testsuite(check-sycl-xrt "Running the SYCL regression tests for sycl-vitis hw_emu"
+add_lit_testsuite(check-sycl-vitis-xrt "Running the SYCL regression tests for sycl-vitis hw_emu"
   ${CMAKE_CURRENT_BINARY_DIR}/vitis
   ARGS ${RT_TEST_ARGS}
   PARAMS "VITIS=only;SYCL_TRIPLE=fpga64_hls_hw_emu-xilinx-linux;SYCL_PLUGIN=xrt"
   DEPENDS ${SYCL_TEST_DEPS}
   EXCLUDE_FROM_CHECK_ALL
   )
-set_target_properties(check-sycl-xrt PROPERTIES FOLDER "SYCL tests")
+set_target_properties(check-sycl-vitis-xrt PROPERTIES FOLDER "SYCL tests")
 
-add_lit_testsuite(check-sycl-vitis-hw "Running the SYCL regression tests for sycl-vitis hw"
+add_lit_testsuite(check-sycl-vitis-opencl-hw "Running the SYCL regression tests for sycl-vitis hw"
   ${CMAKE_CURRENT_BINARY_DIR}/vitis
   ARGS ${RT_TEST_ARGS}
   PARAMS "VITIS=only;SYCL_TRIPLE=fpga64_hls_hw-xilinx-linux;SYCL_PLUGIN=opencl"
   DEPENDS ${SYCL_TEST_DEPS}
   EXCLUDE_FROM_CHECK_ALL
   )
-set_target_properties(check-sycl-vitis PROPERTIES FOLDER "SYCL tests")
+set_target_properties(check-sycl-vitis-opencl-hw PROPERTIES FOLDER "SYCL tests")
 
-add_lit_testsuite(check-sycl-xrt-hw "Running the SYCL regression tests for sycl-vitis hw"
+add_lit_testsuite(check-sycl-vitis-xrt-hw "Running the SYCL regression tests for sycl-vitis hw"
   ${CMAKE_CURRENT_BINARY_DIR}/vitis
   ARGS ${RT_TEST_ARGS}
   PARAMS "VITIS=only;SYCL_TRIPLE=fpga64_hls_hw-xilinx-linux;SYCL_PLUGIN=xrt"
   DEPENDS ${SYCL_TEST_DEPS}
   EXCLUDE_FROM_CHECK_ALL
   )
-set_target_properties(check-sycl-xrt PROPERTIES FOLDER "SYCL tests")
+set_target_properties(check-sycl-vitis-xrt-hw PROPERTIES FOLDER "SYCL tests")
 
 add_custom_target(check-sycl)
 add_dependencies(check-sycl check-sycl-spirv)