[SYCL] Fix edge_detection and add it to the lit test-suite #87
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keryell
reviewed
Sep 30, 2020
| @@ -92,10 +101,10 @@ int main(int argc, char* argv[]) { | |||
| // to parallel_fors with local sizes | |||
| [=]() { | |||
| auto gX = xilinx::partition_array<char, 9, | |||
| xilinx::partition::complete<0>>({-1, 0, 1, -2, 0, 2, -1, 0, 1}); | |||
| xilinx::partition::complete<1>>({-1, 0, 1, -2, 0, 2, -1, 0, 1}); | |||
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Curious this change.
Are you changing the API?
Do you think it is better to start at 1?
| @@ -258,13 +266,25 @@ def getDeviceCount(device_type): | |||
| if xocc == "only": | |||
| config.name = 'SYCL-XOCC' | |||
| config.test_source_root = config.test_source_root + "/xocc_tests" | |||
| run_if_hw="echo" | |||
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At least add some motivating comments
| @@ -59,7 +53,7 @@ void dataflow(T functor) { | |||
| pipeline way. | |||
| */ | |||
| template <typename T> | |||
| SYCL_DEVICE_ANNOTATE("xilinx_pipeline") __attribute__((always_inline)) | |||
| __SYCL_DEVICE_ANNOTATE("xilinx_pipeline") __attribute__((always_inline)) | |||
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Could even be __TRISYCL prefix to reduce conflicts with Intel or other SYCL implementations
| @@ -348,78 +348,6 @@ struct InSPIRation : public ModulePass { | |||
| } | |||
| } | |||
|
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| /// This currently looks through the arguments passed to the SSDM intrinsic | |||
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edge_detection was failing because of the first argument was expected of xilinx_partition_array was in the generic address space instead of the default/stack address space.
I also added edge_detection to the test-suite it will run only if opencv4 is found and will only compile in hw_emu because images are too large datasets.