Apply Yimin Gu's fixes to elf2flt to allow riscv 32 to use the same

relocation mechansims as riscv 64.

Original copy was passed around the buildroot list, but, it would
be helpful for this to be upstream.  cnlohr <[email protected]> rebased it.

You can see the original patch here:

5330503

Below is the contents of the original patch:

From 599e31157815a6e82d920693fafea249ef95dfc7 Mon Sep 17 00:00:00 2001
From: Yimin Gu <[email protected]>
Date: Thu, 17 Nov 2022 21:16:28 +0900
Subject: [PATCH] Added RISC-V 32-bit compilation support

Let elf2flt compile for RISC-V 32-bit targets. With these changes, the
uclibc toolchain and busybox can work fine for rv32 no MMU systems with
no noticable problem.

and

From 3f1f323 Mon Sep 17 00:00:00 2001
From: Damien Le Moal <[email protected]>
Date: Wed, 9 Sep 2020 17:31:33 +0900
Subject: [PATCH] elf2flt: add riscv 64-bits support

Add support for riscv 64bits ISA by defining the relocation types
R_RISCV_32_PCREL, R_RISCV_ADD32, R_RISCV_SUB32, R_RISCV_32 and
R_RISCV_64. riscv64 support also needs the __global_pointer$ symbol to
be defined right after the relocation tables in the data section. To
define this symbol, the "RISCV_GP" line prefix is added. The "RISCV_GP"
string is removed if the target CPU type is riscv64 and the definition
line is dropped for other CPU types.

With these changes, buildroot and busybox build and run on riscv NOMMU
systems with Linux kernel including patch 6045ab5fea4c
("binfmt_flat: do not stop relocating GOT entries prematurely on riscv")
fixing the binfmt_flat loader. Tested on QEMU and Canaan Kendryte K210
boards.

This patch is based on earlier work by Christoph Hellwig <[email protected]>.

Signed-off-by: Damien Le Moal <[email protected]>

elf2flt.c

@@ -81,7 +81,7 @@ const char *elf2flt_progname;
 #include <elf/v850.h>
 #elif defined(TARGET_xtensa)
 #include <elf/xtensa.h>
-#elif defined(TARGET_riscv64)
+#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
 #include <elf/riscv.h>
 #endif
 
@@ -127,6 +127,8 @@ const char *elf2flt_progname;
 #define ARCH	"xtensa"
 #elif defined(TARGET_riscv64)
 #define ARCH	"riscv64"
+#elif defined(TARGET_riscv32)
+#define ARCH	"riscv32"
 #else
 #error "Don't know how to support your CPU architecture??"
 #endif
@@ -822,7 +824,7 @@ output_relocs (
 					goto good_32bit_resolved_reloc_update_text;
 				default:
 					goto bad_resolved_reloc;
-#elif defined(TARGET_riscv64)
+#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
 				case R_RISCV_NONE:
 				case R_RISCV_32_PCREL:
 				case R_RISCV_ADD8:

ld-elf2flt.c

@@ -327,7 +327,7 @@ static int do_final_link(void)
 	/* riscv adds a global pointer symbol to the linker file with the
 	   "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
 	   the entire line for other architectures. */
-	if (streq(TARGET_CPU, "riscv64"))
+	if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
 		append_sed(&sed, "^RISCV_GP:", "");
 	else
 		append_sed(&sed, "^RISCV_GP:", NULL);