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Fix merge.
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thealmarty committed Jan 15, 2024
1 parent b087138 commit 12adcc3
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Showing 3 changed files with 29 additions and 46 deletions.
2 changes: 0 additions & 2 deletions alu_u32/src/com/columns.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,6 @@ pub struct Com32Cols<T> {

pub is_ne: T,
pub is_eq: T,
pub is_ne: T,
pub is_eq: T,
}

pub const NUM_COM_COLS: usize = size_of::<Com32Cols<u8>>();
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66 changes: 28 additions & 38 deletions alu_u32/src/com/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,14 @@ use core::iter;
use core::mem::transmute;
use valida_bus::MachineWithGeneralBus;
use valida_cpu::MachineWithCpuChip;
use valida_machine::config::StarkConfig;
use valida_machine::{
instructions, Chip, Instruction, Interaction, Operands, Word, MEMORY_CELL_BYTES,
};
use valida_opcodes::{EQ32, NE32};

use p3_air::VirtualPairCol;
use p3_field::PrimeField;
use p3_field::{AbstractField, Field, PrimeField};
use p3_matrix::dense::RowMajorMatrix;
use p3_maybe_rayon::*;
use valida_util::pad_to_power_of_two;
Expand All @@ -25,20 +26,19 @@ pub mod stark;
pub enum Operation {
Ne32(Word<u8>, Word<u8>, Word<u8>), // (dst, src1, src2)
Eq32(Word<u8>, Word<u8>, Word<u8>), // (dst, src1, src2)
Eq32(Word<u8>, Word<u8>, Word<u8>), // (dst, src1, src2)
}

#[derive(Default)]
pub struct Com32Chip {
pub operations: Vec<Operation>,
}

impl<F, M> Chip<M> for Com32Chip
impl<M, SC> Chip<M, SC> for Com32Chip
where
F: PrimeField,
M: MachineWithGeneralBus<F = F>,
M: MachineWithGeneralBus<SC::Val>,
SC: StarkConfig,
{
fn generate_trace(&self, _machine: &M) -> RowMajorMatrix<M::F> {
fn generate_trace(&self, _machine: &M) -> RowMajorMatrix<SC::Val> {
let rows = self
.operations
.par_iter()
Expand All @@ -48,30 +48,23 @@ where
let mut trace =
RowMajorMatrix::new(rows.into_iter().flatten().collect::<Vec<_>>(), NUM_COM_COLS);

pad_to_power_of_two::<NUM_COM_COLS, F>(&mut trace.values);
pad_to_power_of_two::<NUM_COM_COLS, SC::Val>(&mut trace.values);

trace
}

fn global_receives(&self, machine: &M) -> Vec<Interaction<M::F>> {
let opcode = VirtualPairCol::new_main(
vec![
(COM_COL_MAP.is_ne, M::F::from_canonical_u32(NE32)),
(COM_COL_MAP.is_eq, M::F::from_canonical_u32(EQ32)),
],
M::F::zero(),
);
fn global_receives(&self, machine: &M) -> Vec<Interaction<SC::Val>> {
let opcode = VirtualPairCol::new_main(
vec![
(COM_COL_MAP.is_ne, M::F::from_canonical_u32(NE32)),
(COM_COL_MAP.is_eq, M::F::from_canonical_u32(EQ32)),
(COM_COL_MAP.is_ne, SC::Val::from_canonical_u32(NE32)),
(COM_COL_MAP.is_eq, SC::Val::from_canonical_u32(EQ32)),
],
M::F::zero(),
SC::Val::zero(),
);
let input_1 = COM_COL_MAP.input_1.0.map(VirtualPairCol::single_main);
let input_2 = COM_COL_MAP.input_2.0.map(VirtualPairCol::single_main);
let output = (0..MEMORY_CELL_BYTES - 1)
.map(|_| VirtualPairCol::constant(M::F::zero()))
.map(|_| VirtualPairCol::constant(SC::Val::zero()))
.chain(iter::once(VirtualPairCol::single_main(COM_COL_MAP.output)));

let mut fields = vec![opcode];
Expand All @@ -84,7 +77,6 @@ where
let receive = Interaction {
fields,
count: is_real,
count: is_real,
argument_index: machine.general_bus(),
};
vec![receive]
Expand All @@ -111,22 +103,22 @@ impl Com32Chip {
}
}

pub trait MachineWithCom32Chip: MachineWithCpuChip {
pub trait MachineWithCom32Chip<F: Field>: MachineWithCpuChip<F> {
fn com_u32(&self) -> &Com32Chip;
fn com_u32_mut(&mut self) -> &mut Com32Chip;
}

instructions!(Ne32Instruction, Eq32Instruction);
instructions!(Ne32Instruction, Eq32Instruction);

impl<M> Instruction<M> for Ne32Instruction
impl<M, F> Instruction<M, F> for Ne32Instruction
where
M: MachineWithCom32Chip,
M: MachineWithCom32Chip<F>,
F: Field,
{
const OPCODE: u32 = NE32;

fn execute(state: &mut M, ops: Operands<i32>) {
let opcode = <Self as Instruction<M>>::OPCODE;
let opcode = <Self as Instruction<M, F>>::OPCODE;
let clk = state.cpu().clock;
let pc = state.cpu().pc;
let mut imm: Option<Word<u8>> = None;
Expand Down Expand Up @@ -157,36 +149,36 @@ where
.com_u32_mut()
.operations
.push(Operation::Ne32(dst, src1, src2));
state
.com_u32_mut()
.operations
.push(Operation::Eq32(dst, src1, src2));
state.cpu_mut().push_bus_op(imm, opcode, ops);
}
}


impl<M> Instruction<M> for Eq32Instruction
impl<M, F> Instruction<M, F> for Eq32Instruction
where
M: MachineWithCom32Chip,
M: MachineWithCom32Chip<F>,
F: Field,
{
const OPCODE: u32 = EQ32;

fn execute(state: &mut M, ops: Operands<i32>) {
let opcode = <Self as Instruction<M>>::OPCODE;
let opcode = <Self as Instruction<M, F>>::OPCODE;
let clk = state.cpu().clock;
let pc = state.cpu().pc;
let mut imm: Option<Word<u8>> = None;
let read_addr_1 = (state.cpu().fp as i32 + ops.b()) as u32;
let write_addr = (state.cpu().fp as i32 + ops.a()) as u32;
let src1 = state.mem_mut().read(clk, read_addr_1, true, pc, opcode, 0, "");
let src1 = state
.mem_mut()
.read(clk, read_addr_1, true, pc, opcode, 0, "");
let src2 = if ops.is_imm() == 1 {
let c = (ops.c() as u32).into();
imm = Some(c);
c
} else {
let read_addr_2 = (state.cpu().fp as i32 + ops.c()) as u32;
state.mem_mut().read(clk, read_addr_2, true, pc, opcode, 1, "")
state
.mem_mut()
.read(clk, read_addr_2, true, pc, opcode, 1, "")
};

let dst = if src1 == src2 {
Expand All @@ -200,8 +192,6 @@ where
.com_u32_mut()
.operations
.push(Operation::Eq32(dst, src1, src2));
state
.cpu_mut()
.push_bus_op(imm, opcode, ops);
state.cpu_mut().push_bus_op(imm, opcode, ops);
}
}
7 changes: 1 addition & 6 deletions basic/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,6 @@ use valida_alu_u32::{
com::{Com32Chip, Eq32Instruction, MachineWithCom32Chip, Ne32Instruction},
div::{Div32Chip, Div32Instruction, MachineWithDiv32Chip, SDiv32Instruction},
lt::{Lt32Chip, Lt32Instruction, MachineWithLt32Chip},
com::{Com32Chip, Ne32Instruction, Eq32Instruction, MachineWithCom32Chip},
mul::{
MachineWithMul32Chip, Mul32Chip, Mul32Instruction, Mulhs32Instruction, Mulhu32Instruction,
},
Expand Down Expand Up @@ -92,8 +91,6 @@ pub struct BasicMachine<F: PrimeField32 + TwoAdicField> {
ne32: Ne32Instruction,
#[instruction(com_u32)]
eq32: Eq32Instruction,
#[instruction(com_u32)]
eq32: Eq32Instruction,
#[instruction(bitwise_u32)]
and32: And32Instruction,
#[instruction(bitwise_u32)]
Expand Down Expand Up @@ -260,9 +257,7 @@ impl<F: PrimeField32 + TwoAdicField> MachineWithCom32Chip<F> for BasicMachine<F>
}
}

impl<F: PrimeField64 + TwoAdicField, EF: ExtensionField<F>> MachineWithShift32Chip
for BasicMachine<F, EF>
{
impl<F: PrimeField32 + TwoAdicField> MachineWithShift32Chip<F> for BasicMachine<F> {
fn shift_u32(&self) -> &Shift32Chip {
&self.shift_u32
}
Expand Down

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