[LOGGING] Fixed LUT Sizing Issue #153

Job	Run time
Run-tests (vtr_reg_nightly_test1, 16)	2h 3m 12s
Run-tests (vtr_reg_nightly_test1_odin, 16, -DWITH_ODIN=ON)	3h 36m 16s
Run-tests (vtr_reg_nightly_test2, 16)	3h 56m 7s
Run-tests (vtr_reg_nightly_test2_odin, 16, -DWITH_ODIN=ON)	3h 40m 32s
Run-tests (vtr_reg_nightly_test3, 16)	1h 56m 1s
Run-tests (vtr_reg_nightly_test3_odin, 16, -DWITH_ODIN=ON)	3h 25m 37s
Run-tests (vtr_reg_nightly_test4, 16)	3h 0m 5s
Run-tests (vtr_reg_nightly_test4_odin, 16, -DWITH_ODIN=ON)	1h 14m 42s
Run-tests (vtr_reg_nightly_test5, 16)	3h 9m 34s
Run-tests (vtr_reg_nightly_test6, 16)	3h 45m 34s
Run-tests (vtr_reg_nightly_test7, 16)	51m 24s
Run-tests (vtr_reg_strong, 16, -DVTR_ASSERT_LEVEL=3, libeigen3-dev)	15m 38s
Run-tests (vtr_reg_strong_odin, 16, -DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON, libeigen3-dev)	20m 5s
Run-tests (vtr_reg_strong_odin, 16, -skip_qor, -DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWI...	1h 10m 2s
Run-tests (vtr_reg_system_verilog, 16, -DYOSYS_F4PGA_PLUGINS=ON)	22m 2s
Run-tests (odin_reg_strong, 16, -DWITH_ODIN=ON)	1h 0m 49s
Run-tests (parmys_reg_strong, 16, -DYOSYS_F4PGA_PLUGINS=ON)	2h 42m 35s
	1d 12h 30m 15s

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