new golden result

verilog-to-routing · Aug 2, 2024 · 0222054 · 0222054
1 parent ad6a905
commit 0222054
Show file tree

Hide file tree

Showing 3 changed files with 253 additions and 478 deletions.
diff --git a/parmys/regression_test/benchmark/task/koios/koios_proxy_no_hb/synthesis_result.json b/parmys/regression_test/benchmark/task/koios/koios_proxy_no_hb/synthesis_result.json
@@ -348,10 +348,10 @@
             "Ignoring module tanh because it contains processes (run 'proc' command first).",
             "Ignoring module xor_module because it contains processes (run 'proc' command first)."
         ],
-        "elaboration_time(ms)": 433.6,
-        "optimization_time(ms)": 1594.8,
-        "techmap_time(ms)": 1885.6,
-        "synthesis_time(ms)": 3914.2,
+        "elaboration_time(ms)": 305,
+        "optimization_time(ms)": 1212.8,
+        "techmap_time(ms)": 881.9,
+        "synthesis_time(ms)": 2399.8,
         "Pi": 938,
         "Po": 175,
         "logic element": 67048,
@@ -511,10 +511,10 @@
             "Ignoring module tensor_block because it contains processes (run 'proc' command first).",
             "Ignoring module xor_module because it contains processes (run 'proc' command first)."
         ],
-        "elaboration_time(ms)": 1621.3,
-        "optimization_time(ms)": 1123.3,
-        "techmap_time(ms)": 5526.4,
-        "synthesis_time(ms)": 8271.2,
+        "elaboration_time(ms)": 786.7,
+        "optimization_time(ms)": 442.6,
+        "techmap_time(ms)": 1739,
+        "synthesis_time(ms)": 2968.4,
         "Pi": 318,
         "Po": 256,
         "logic element": 626810,
@@ -798,10 +798,10 @@
             "Ignoring module tensor_block_bf16 because it contains processes (run 'proc' command first).",
             "Ignoring module xor_module because it contains processes (run 'proc' command first)."
         ],
-        "elaboration_time(ms)": 431.2,
-        "optimization_time(ms)": 1447.2,
-        "techmap_time(ms)": 1766.9,
-        "synthesis_time(ms)": 3645.5,
+        "elaboration_time(ms)": 306.5,
+        "optimization_time(ms)": 1022,
+        "techmap_time(ms)": 769.8,
+        "synthesis_time(ms)": 2098.5,
         "Pi": 732,
         "Po": 304,
         "logic element": 130765,
@@ -833,7 +833,6 @@
     "koios_proxy_no_hb/proxy.4/k6FracN10LB_mem20K_complexDSP_customSB_22nm": {
         "test_name": "koios_proxy_no_hb/proxy.4/k6FracN10LB_mem20K_complexDSP_customSB_22nm",
         "architecture": "k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml",
-        "exit": 137,
         "warnings": [
             "Ignoring module FpAddSub_b_dspchain because it contains processes (run 'proc' command first).",
             "Ignoring module FPAddSub_a_dspchain because it contains processes (run 'proc' command first).",
@@ -1247,10 +1246,10 @@
             "Ignoring module systolic_data_setup_systolic_8x8 because it contains processes (run 'proc' command first).",
             "Ignoring module xor_module because it contains processes (run 'proc' command first)."
         ],
-        "elaboration_time(ms)": 85.1,
-        "optimization_time(ms)": 133.6,
-        "techmap_time(ms)": 357.2,
-        "synthesis_time(ms)": 576,
+        "elaboration_time(ms)": 75.5,
+        "optimization_time(ms)": 125.5,
+        "techmap_time(ms)": 242,
+        "synthesis_time(ms)": 443.1,
         "Pi": 465,
         "Po": 320,
         "logic element": 15584,
@@ -1619,10 +1618,10 @@
             "Ignoring module tensor_block because it contains processes (run 'proc' command first).",
             "Ignoring module xor_module because it contains processes (run 'proc' command first)."
         ],
-        "elaboration_time(ms)": 377.3,
-        "optimization_time(ms)": 586.3,
-        "techmap_time(ms)": 1526.1,
-        "synthesis_time(ms)": 2489.9,
+        "elaboration_time(ms)": 546.3,
+        "optimization_time(ms)": 1288.8,
+        "techmap_time(ms)": 1128,
+        "synthesis_time(ms)": 2963.2,
         "Pi": 605,
         "Po": 420,
         "logic element": 161045,
@@ -1876,10 +1875,10 @@
             "Ignoring module systolic_data_setup_systolic_4x4_fp because it contains processes (run 'proc' command first).",
             "Ignoring module xor_module because it contains processes (run 'proc' command first)."
         ],
-        "elaboration_time(ms)": 373.9,
-        "optimization_time(ms)": 1011.4,
-        "techmap_time(ms)": 1465.7,
-        "synthesis_time(ms)": 2851.2,
+        "elaboration_time(ms)": 415.5,
+        "optimization_time(ms)": 1073.5,
+        "techmap_time(ms)": 851.3,
+        "synthesis_time(ms)": 2340.4,
         "Pi": 354,
         "Po": 144,
         "logic element": 90388,
@@ -2116,10 +2115,10 @@
             "Ignoring module systolic_data_setup because it contains processes (run 'proc' command first).",
             "Ignoring module systolic_data_setup_systolic_8x8 because it contains processes (run 'proc' command first)."
         ],
-        "elaboration_time(ms)": 247,
-        "optimization_time(ms)": 280.9,
-        "techmap_time(ms)": 924.8,
-        "synthesis_time(ms)": 1452.9,
+        "elaboration_time(ms)": 248.7,
+        "optimization_time(ms)": 244.9,
+        "techmap_time(ms)": 793.2,
+        "synthesis_time(ms)": 1286.9,
         "Pi": 346,
         "Po": 656,
         "logic element": 90035,

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt
@@ -1,5 +1,5 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	 
- k4_N10_memSize16384_memData64.xml	  ch_intrinsics.v	  common	  1.80	  vpr	  62.16 MiB	  	  -1	  -1	  0.23	  21952	  3	  0.05	  -1	  -1	  37108	  -1	  -1	  70	  99	  1	  0	  success	  v8.0.0-6956-gf669015f3-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-01-27T02:28:44	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  63656	  99	  130	  351	  481	  1	  224	  300	  13	  13	  169	  clb	  auto	  23.7 MiB	  0.04	  527	  62.2 MiB	  0.10	  0.00	  30	  1250	  10	  3.33e+06	  2.22e+06	  408126.	  2414.95	  0.79	 
- k4_N10_memSize16384_memData64.xml	  diffeq1.v	  common	  4.74	  vpr	  66.30 MiB	  	  -1	  -1	  0.34	  26676	  23	  0.30	  -1	  -1	  37692	  -1	  -1	  69	  162	  0	  5	  success	  v8.0.0-6956-gf669015f3-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-01-27T02:28:44	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  67888	  162	  96	  1186	  1127	  1	  676	  332	  13	  13	  169	  clb	  auto	  28.3 MiB	  0.14	  4471	  66.3 MiB	  0.13	  0.00	  54	  9470	  21	  3.33e+06	  2.52e+06	  696024.	  4118.48	  2.84	 
- k4_N10_memSize16384_memData64.xml	  single_wire.v	  common	  0.35	  vpr	  59.43 MiB	  	  -1	  -1	  0.05	  19896	  1	  0.01	  -1	  -1	  33124	  -1	  -1	  0	  1	  0	  0	  success	  v8.0.0-6956-gf669015f3-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-01-27T02:28:44	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  60860	  1	  1	  1	  2	  0	  1	  2	  3	  3	  9	  -1	  auto	  20.6 MiB	  0.00	  2	  59.4 MiB	  0.00	  0.00	  2	  2	  1	  30000	  0	  1489.46	  165.495	  0.00	 
- k4_N10_memSize16384_memData64.xml	  single_ff.v	  common	  0.35	  vpr	  59.51 MiB	  	  -1	  -1	  0.06	  20320	  1	  0.00	  -1	  -1	  33480	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-6956-gf669015f3-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-01-27T02:28:44	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  60936	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  20.8 MiB	  0.00	  4	  59.5 MiB	  0.00	  0.00	  16	  5	  1	  30000	  30000	  2550.78	  283.420	  0.00	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	
+k4_N10_memSize16384_memData64.xml	ch_intrinsics.v	common	1.98	vpr	63.65 MiB		-1	-1	0.26	21736	3	0.10	-1	-1	36460	-1	-1	69	99	1	0	success	v8.0.0-10867-ga41a098a9-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.5.0-41-generic x86_64	2024-08-01T00:02:15	amir-virtual-machine	/home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts	65180	99	130	353	483	1	220	299	13	13	169	clb	auto	24.9 MiB	0.04	540	29270	3582	8022	17666	63.7 MiB	0.03	0.00	26	1477	14	3.33e+06	2.19e+06	360896.	2135.48	0.69	
+k4_N10_memSize16384_memData64.xml	diffeq1.v	common	3.62	vpr	67.04 MiB		-1	-1	0.40	26464	23	0.30	-1	-1	38200	-1	-1	71	162	0	5	success	v8.0.0-10867-ga41a098a9-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.5.0-41-generic x86_64	2024-08-01T00:02:15	amir-virtual-machine	/home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts	68648	162	96	1200	1141	1	688	334	13	13	169	clb	auto	29.0 MiB	0.14	4622	86026	24278	56070	5678	67.0 MiB	0.12	0.00	52	9618	18	3.33e+06	2.58e+06	671819.	3975.26	1.39	
+k4_N10_memSize16384_memData64.xml	single_wire.v	common	0.61	vpr	60.93 MiB		-1	-1	0.07	20064	1	0.02	-1	-1	33000	-1	-1	0	1	0	0	success	v8.0.0-10867-ga41a098a9-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.5.0-41-generic x86_64	2024-08-01T00:02:15	amir-virtual-machine	/home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts	62392	1	1	1	2	0	1	2	3	3	9	-1	auto	22.5 MiB	0.00	2	3	3	0	0	60.9 MiB	0.00	0.00	2	2	1	30000	0	1489.46	165.495	0.00	
+k4_N10_memSize16384_memData64.xml	single_ff.v	common	0.63	vpr	60.94 MiB		-1	-1	0.07	20368	1	0.03	-1	-1	33196	-1	-1	1	2	0	0	success	v8.0.0-10867-ga41a098a9-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.5.0-41-generic x86_64	2024-08-01T00:02:15	amir-virtual-machine	/home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts	62404	2	1	3	4	1	3	4	3	3	9	-1	auto	22.5 MiB	0.00	4	9	6	0	3	60.9 MiB	0.00	0.00	16	5	1	30000	30000	2550.78	283.420	0.00